Interposer IC Segmentation for Thermal Management
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Solution Overview
Problem
The integration of increasing functionality onto a single System on a Chip (SOC) leads to significant heat generation challenges, particularly in handheld devices lacking effective cooling mechanisms, limiting high-performance operation time and increasing power consumption.
Innovation Solution
The use of an interposer to separate and spread out high-power and low-power integrated circuits, combined with phase change materials for thermal management, allows for more efficient heat dissipation and optimized power consumption by interleaving high and low leakage current ICs, and incorporating thermal reservoirs to manage peak temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If functionality is integrated onto a single SOC, then device form factor is reduced, but heat generation increases significantly
Solution Approach 1:
The patent divides the SOC into multiple separate integrated circuits (ICs) that are mounted on an interposer substrate. This segmentation allows heat to be distributed across a larger area rather than concentrated on a single die, directly addressing the heat generation problem while maintaining compact form factor through the interposer architecture.
Solution Approach 2:
The patent transitions from a two-dimensional planar SOC layout to a three-dimensional stacked architecture using an interposer. Multiple ICs are arranged in different layers and positions on the interposer, spreading heat generation across multiple spatial dimensions and improving thermal management.
2Productivity
If high performance mode is maintained continuously, then computational capability is maximized, but thermal limits are exceeded
Solution Approach 1:
The patent enables dynamic thermal management by allowing the system to maintain higher performance levels for longer durations through improved heat dissipation. The segmented architecture provides dynamic thermal headroom, allowing flexible adjustment of performance states without immediately hitting thermal walls.
3Ease of operation
If SOC is kept powered up in lower performance state, then readiness is maintained, but power overhead increases
Solution Approach 1:
By segmenting the SOC into separate ICs on an interposer, the patent enables independent power management of different functional blocks. Individual ICs can be powered down or placed in low-power states more granularly, reducing overall power overhead while maintaining system readiness.
4Temperature
If multiple ICs are separated on interposer, then heat dissipation is improved, but device area increases
Solution Approach 1:
The patent merges multiple separate ICs onto a single interposer substrate, consolidating what would otherwise be分散 components into one integrated package. This merging approach improves heat dissipation through spatial separation while avoiding the area penalty of completely separate components.
Solution Approach 2:
The interposer acts as an intermediary substrate that hosts multiple ICs in a compact arrangement. It provides both mechanical support and thermal management functions, enabling efficient heat dissipation while maintaining a compact footprint through its mediator role between the ICs and the final assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables longer operation in high-performance states while reducing overall power consumption and improving energy efficiency, as well as reducing the height of the assembly and enhancing yield by allowing defective ICs to be discarded before assembly.
Implementation Method 1
a phase change material may cover the plurality of integrated circuits and/or may be placed to the side of the integrated circuits, providing a local thermal reservoir reducing peak transient temperature
Implementation Method 2
The ICs may be arranged on the interposer to spread out the potentially high power ICs (e.g. processors) and lower power ICs, interleaving the low power ICs with the high power ICs, in some embodiments. Thus, the heat may be generated over a larger area and may be more readily dissipated
Data Source
AI summary
In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.