Interposer-Based 3D Semiconductor Package for Signal Speed
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently connecting multiple semiconductor chips with different functions within a limited area, leading to bottlenecks in memory devices and requiring a large number of interconnection lines, which can be difficult to achieve with traditional packaging methods.
Innovation Solution
The semiconductor package design includes a first semiconductor chip, a second semiconductor chip overlapping with the first, and an interposer with internal and external interconnectors, along with a dielectric layer, to provide multiple electrical paths and reduce signal transmission time, using through silicon vias (TSVs) and fine-pitch interconnection lines to connect the chips effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional packaging methods are used to connect multiple semiconductor chips, then the structure is simple and easy to manufacture, but the number of interconnection lines required is large and the signal transmission speed is slow
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging, where multiple semiconductor chips are vertically stacked and connected through through-silicon vias (TSVs). This dimensional change allows signal transmission paths to extend through the thickness of the package, significantly reducing lateral interconnection lengths and improving signal transmission speed while enabling higher interconnection density.
Solution Approach 2:
The patent introduces an interposer as an intermediary component between stacked semiconductor chips. The interposer contains redistribution layers and TSVs that route signals between chips, enabling complex interconnection patterns without requiring direct chip-to-chip bonding. This mediator simplifies the overall interconnection structure by centralizing routing functions in the interposer layer.
2Productivity
If more interconnection lines are added to connect multiple chips, then the data transmission rate increases, but the available area for interconnections is limited
Solution Approach 1:
The patent utilizes the vertical dimension by stacking chips and using TSVs to create three-dimensional interconnection paths. This allows numerous interconnection lines to be packed into a small footprint area by routing them through the thickness of the package rather than spreading them out laterally, thereby increasing data transmission rate without proportionally increasing package area.
Solution Approach 2:
The patent employs nested interconnection structures where redistribution layers are embedded within the interposer and chip layers. Multiple interconnection levels are nested vertically, with each layer containing additional interconnection pathways. This nesting approach multiplies the effective interconnection capacity within the same planar footprint, enabling higher data transmission rates in a compact package.
3Quantity of substance
If chips are stacked to increase integration density, then the number of chips per package increases, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent performs preliminary preparation of TSVs, redistribution layers, and bonding pads on each chip and interposer before stacking. This advance preparation allows for standardized, modular assembly where components are pre-configured with their interconnection structures, simplifying the subsequent stacking and bonding processes. The preliminary formation of TSVs and conductive layers enables high-density integration without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor package may include a first semiconductor chip, a second semiconductor chip disposed to overlap with a portion of the first semiconductor chip and connected to the first semiconductor chip through first coupling structures. The semiconductor package may include an interposer disposed to overlap with another portion of the first semiconductor chip and may be connected to the first semiconductor chip through second coupling structures. A first surface of the interposer may face the first semiconductor chip, and the interposer may include second internal interconnectors extending from the second coupling structures on the first surface to a second surface of the interposer opposite to the first face. External interconnectors may be disposed on the second surface of the interposer and are connected to the second internal interconnectors.