Interposer for Hermetic Sensor-Seal and IC Integration
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Solution Overview
Problem
Conventional techniques for integrating sensors and IC chips, such as monolithic, board-level, and package-level integration, face challenges including high costs, increased size, and limited flexibility due to the need for through silicon vias and thick organic package substrates, which restrict packing density and performance.
Innovation Solution
The use of an interposer to hermetically seal sensor chips and provide electrical coupling with IC chips, allowing multiple sensor chips to be mounted on the same interposer with a hermetic seal, eliminating the need for expensive through silicon vias and reducing physical size by eliminating the organic package substrate, while enabling closer interconnect lengths akin to monolithic integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If package-level integration is used with organic package substrate, then sensors and IC chips can be integrated, but the physical size increases significantly
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the sensor chip and IC chip. This interposer provides a platform for integrating multiple chips while maintaining compact dimensions, eliminating the need for thick organic package substrates. The interposer enables direct bonding of chips on opposite sides, reducing overall package size while preserving integration capability.
2Reliability
If through silicon via (TSV) is formed for electrical connections, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The interposer serves as a mediator that provides electrical interconnection between sensor chips and IC chips without requiring TSV formation through thick substrates. The interposer contains built-in interconnect structures that simplify the manufacturing process, eliminating complex TSV fabrication steps while maintaining reliable electrical connectivity.
3Ease of manufacture
If monolithic integration is used, then cost is reduced and interconnect length is minimized, but fabrication complexity increases and flexibility decreases
Solution Approach 1:
The patent segments the integration into separate components (sensor chip, interposer, IC chip) that can be independently fabricated and then bonded together. This segmentation allows each component to be optimized separately, maintaining the cost benefits of separate fabrication while achieving compact integration comparable to monolithic solutions. The modular approach also preserves flexibility for different sensor and IC combinations.
4Ease of operation
If board-level integration is used, then assembly is straightforward, but packing density decreases due to package thickness
Solution Approach 1:
The patent transitions from planar board-level integration to three-dimensional integration by bonding chips on opposite sides of the interposer. This vertical stacking approach dramatically increases packing density while maintaining straightforward assembly processes. Multiple chips are integrated in the thickness dimension rather than spreading them out on a large substrate area.
Data Source
AI summary
Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.