Interposer Shielded Contacts Sub-400 Micron Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electrical connectors face challenges in making separable connections for semiconductor devices with decreasing contact pitch, especially below 400 microns, and struggle with high-speed signal integrity due to noise and crosstalk issues, which are exacerbated by the need for additional PCB area and increased pin count.
Innovation Solution
The development of an interposer with shielded contact probes and traces that include signal pins electrically coupled to ground pins and inner ground planes, providing effective shielding without increasing the connector size, using a multi-layered structure with conductive layers and isolation substrates to reduce crosstalk and improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional techniques are used to make separable electrical connections, then connections can be made between electronic components, but the pitch must be 400 microns or more, making connections below 400 microns prohibitively difficult and expensive
Solution Approach 1:
The patent transitions from a two-dimensional planar connector design to a three-dimensional stacked interposer architecture. Multiple contact arrays are arranged in vertical stacks with different orientations (e.g., first contact array in a first plane, second contact array in a second plane), enabling high-density connections at sub-400-micron pitch by utilizing the third dimension for spatial organization of contacts and routing paths.
2Reliability
If grounded contact elements are positioned between every adjacent pair of differential signal pins to reduce crosstalk noise, then signal integrity improves, but pin count and connector size increase
Solution Approach 1:
The patent combines multiple functions into shared structures: ground planes serve as both shielding elements for crosstalk reduction and as electrical connection paths between contact arrays. The interposer substrate integrates multiple contact arrays, routing paths, and ground planes into a single compact structure, eliminating the need for separate grounded contact elements between each differential pair while maintaining signal integrity.
Solution Approach 2:
The patent uses vertical stacking to separate signal paths from ground elements in the third dimension. Contact arrays are positioned in different planes with routing paths connecting them through the interposer thickness, allowing ground planes to provide shielding without occupying lateral space that would increase pin count. The z-dimension enables dense lateral packing while maintaining adequate spacing for signal integrity.
3Device complexity
If high-speed differential signal pairs are placed in adjacent positions, then pin count decreases, but noise easily transfers from one differential pair to neighboring differential pair
Solution Approach 1:
The patent introduces ground planes as intermediary elements between adjacent differential signal pairs. These ground planes act as electromagnetic shields that intercept and divert noise fields, preventing direct coupling between neighboring signal pairs. The ground planes are strategically positioned within the interposer structure to provide shielding without increasing the overall connector footprint.
4Reliability
If shielded contact elements are implemented, then crosstalk is reduced, but connector size increases
Solution Approach 1:
The patent resolves the area conflict by moving shielding functions to the vertical dimension. Ground planes are positioned at different heights within the interposer stack, providing three-dimensional shielding coverage. This vertical arrangement allows lateral contact pitch to be minimized for high density while maintaining effective shielding distances in the z-direction, preventing the need for increased lateral connector area.
Data Source
AI summary
A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. Embodiments provide one or more signal pins in a contact array electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins. These buried ground layers provide additional crosstalk isolation in close proximity to signal pins, resulting in improved signal integrity in a significantly reduced space.