Interposer Side Surface Conductive Pattern for PCB Test Points
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Solution Overview
Problem
The challenge in electronic devices is to efficiently arrange and connect multiple printed circuit boards (PCBs) while providing a test point for electrical elements without increasing the device's size, which is hindered by the need for additional test points and conductive vias that occupy valuable space.
Innovation Solution
An electronic device design incorporating an interposer with a dielectric substrate and conductive vias that electrically connects two PCBs, featuring a conductive pattern on its side surface to serve as a test point, allowing for performance testing without increasing the interposer's volume or occupying additional space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test point is added on the PCB using an interposer, then performance testing of electrical elements becomes possible, but the volume of the interposer increases due to the addition of a conductive via
Solution Approach 1:
The patent moves the test point from the traditional PCB surface (2D plane) to the side surface of the interposer (3D space). By forming a conductive pattern on the lateral surface of the interposer that extends from the first PCB to the second PCB, the test point is positioned in a different spatial dimension, allowing testing without increasing the interposer's length or width.
Solution Approach 2:
The interposer serves multiple functions: it electrically connects the first PCB and second PCB through conductive vias, provides mechanical support and spacing between the PCBs, and simultaneously serves as the test point structure through its side surface conductive pattern. This multi-functionality eliminates the need for separate test point structures that would increase volume.
2Length of moving object
If multiple PCBs are arranged in a stacked manner to secure efficient mounting space, then the device becomes slimmer, but the design freedom for test points and peripheral components is reduced
Solution Approach 1:
By utilizing the side surface of the interposer for the test point conductive pattern, the invention creates an additional testing dimension that does not consume area on the PCB stacking planes. This allows the stacked PCB arrangement to remain compact while maintaining test point functionality.
Solution Approach 2:
The interposer is segmented into distinct functional zones: top surface for connecting to first PCB, bottom surface for connecting to second PCB, and side surface for test point functionality. This segmentation allows each function to be optimized independently without compromising the others, maintaining both compactness and design freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient electrical connection and performance testing of PCBs while maintaining a slim design, enhancing the freedom for mounting electrical elements without enlarging the device's dimensions.
Implementation Method 1
a plurality of conductive vias formed to penetrate from the first substrate surface of the dielectric substrate to the second substrate surface, and electrically connecting the plurality of first conductive terminals to the plurality of second conductive terminals
Implementation Method 2
a first conductive pattern formed from at least a portion of the substrate side surface to the first PCB, wherein the first conductive pattern may be electrically connected to a first conductive pad formed on the first PCB and electrically connected to the at least one first electrical element
Data Source
AI summary
Provided is an electronic device. The electronic device may include a housing; a first printed circuit board (PCB) disposed in an internal space of the housing and including a plurality of first conductive terminals; a second PCB arranged parallel to the first PCB in the internal space, and including a plurality of second conductive terminals; and an interposer disposed between the first PCB and the second PCB to electrically connect the first PCB and the second PCB, the interposer including: a dielectric substrate including a first substrate surface facing the first PCB, a second substrate surface facing the second PCB, and a substrate side surface surrounding a space between the first substrate surface and the second substrate surface; a plurality of conductive vias formed to penetrate from the first substrate surface of the dielectric substrate to the second substrate surface, and electrically connecting the plurality of first conductive terminals to the plurality of second conductive terminals; and a first conductive pattern formed from at least a portion of the substrate side surface to the first PCB, wherein the first conductive pattern may be electrically connected to a first conductive pad formed on the first PCB and electrically connected to the at least one first electrical element.