Interposer Reduces Package Height and Signal Interference

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Solution Overview

Problem

In package-on-package (PoP) semiconductor devices, the limited surface area for circuit layout leads to signal interference between closely positioned circuit paths, and increasing the number of layers in a multi-layered substrate to mitigate this issue increases manufacturing costs.

Innovation Solution

The use of an interposer that provides electrical coupling between substrate contacts and semiconductor chip edges, allowing for additional circuit pathways without the need for additional substrate layers, thereby reducing manufacturing costs and signal interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the number of layers in a multi-layered substrate is increased to reduce signal interference, then signal interference is reduced, but manufacturing cost increases

Engineering Contradiction:
Improvesignal interferenceVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent introduces an interposer layer positioned between the substrate and the semiconductor chip, creating a new dimensional plane for circuit routing. This interposer enables signals to travel through a third dimension (via vertical vias through the interposer) rather than being constrained to horizontal routing only on the substrate layers, effectively adding a new routing dimension that reduces signal interference without requiring additional substrate layers

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer serves as an intermediary component that mediates the electrical connection between the substrate and the semiconductor chip. It provides alternative signal pathways and routing options that are distinct from the substrate's circuit layers, allowing signals to be routed through the interposer's conductive vias and traces, thereby reducing signal interference on the substrate without increasing substrate layer count

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If circuit paths are positioned closer together to increase circuit density, then circuit density increases, but signal interference occurs

Engineering Contradiction:
Improvecircuit densityVSAvoidsignal interference
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The interposer enables vertical signal routing through its thickness via conductive vias, allowing circuit paths to be separated in the vertical dimension while maintaining high horizontal circuit density. This three-dimensional routing capability permits closer spacing of circuit elements on the substrate without increasing signal interference, as signals can transition to different vertical planes within the interposer

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Object-affected harmful factors

If the surface area for circuit layout is increased to reduce signal interference, then signal interference is reduced, but package footprint increases

Engineering Contradiction:
Improvesignal interferenceVSAvoidpackage footprint
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

By utilizing the vertical dimension through the interposer's thickness for signal routing via vias, the patent reduces the need for extended horizontal trace lengths that would be required to achieve the same signal separation on a single plane. This enables signal interference reduction without proportionally increasing the package's surface footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8823156B2Semiconductor device packages having stacking functionality and including interposer
Publication Date: 2014.09.02 ADVANCED SEMICON ENG INC
  • US8823156B2 patent drawing
  • US8823156B2 patent drawing
  • US8823156B2 patent drawing

AI summary

A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.