Interposer Signal Layout With Ground Shielding Around Embedded Vias

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In interposer devices, embedding vias disrupts the regular arrangement of signal and ground lines, leading to weakened shielding and increased manufacturing difficulty and cost, particularly in 2.5D interposer packaging.

Innovation Solution

The interposer device incorporates L-shaped signal lines and L-shaped or F-shaped ground lines in bump regions, maintaining a regular arrangement while ensuring high signal density and effective shielding, with signal lines and ground lines embedded in bump and channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vias are embedded to connect dies on the top layer to signal lines on different layers, then electrical connection between layers is achieved, but the regular arrangement of signal lines and ground lines is disrupted, weakening the shielding effect

Engineering Contradiction:
Improveshielding effectVSAvoidarrangement regularity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a fourth metal layer above the third metal layer to accommodate vias that connect to bumps. By stacking metal layers in multiple dimensions (first through fourth metal layers with vias penetrating through them), the design allows vertical via connections without disrupting the horizontal regular arrangement of signal and ground lines in each layer. This multi-dimensional layering resolves the conflict between achieving electrical connectivity and maintaining shielding effectiveness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If parts of ground lines or signal lines are cut off or paths are changed to provide space for embedding vias, then via embedding is enabled, but manufacturing difficulty and cost increase

Engineering Contradiction:
Improvemanufacturing difficultyVSAvoidline path complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent divides the interposer structure into multiple segmented metal layers (first, second, third, and fourth metal layers), each containing complete, unbroken signal and ground lines arranged in regular patterns. Vias are embedded within these segmented layers or penetrate through them, eliminating the need to cut or bend lines. This segmentation allows via embedding while maintaining simple, regular line paths in each layer, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If multiple dies are arranged on the substrate through an interposer device to increase signal density, then overall signal density increases, but maintaining signal stability becomes more challenging due to potential interference

Engineering Contradiction:
Improvesignal densityVSAvoidsignal stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent employs multiple stacked metal layers (first through fourth metal layers) with regular alternating arrangements of signal lines and ground lines. This multi-layer vertical structure increases signal density by utilizing the third dimension while maintaining effective shielding through consistent ground line placement in each layer. The regular alternating pattern across multiple layers ensures signal stability by preventing interference even as signal density increases.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12506057B2Interposer device and semiconductor package structure
Publication Date: 2025.12.23 GLOBAL UNICHIP CORPORATION
  • US12506057B2 patent drawing
  • US12506057B2 patent drawing
  • US12506057B2 patent drawing

AI summary

An interposer device comprises two bump regions, a channel region, a plurality of signal lines and a plurality of ground lines. The two bump regions are respectively coupled to two semiconductor devices. The channel region is connected between the two bump regions. The plurality of signal lines are embedded in the two bump regions and the channel region, and electrically connected to the two semiconductor devices for transmitting circuit signals. The plurality of ground lines are embedded in the two bump regions and the channel region for shielding the plurality of signal lines. In each bump region, each signal line comprises a trunk portion, a turning portion, and a signal turning point connected between the trunk portion and the turning portion. The trunk portion extends parallel to a first direction, and the turning portion extends parallel to a second direction.