Interposer Package Structure with Silicon Bridge Interconnects
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Solution Overview
Problem
Existing semiconductor packaging structures are inadequate in providing efficient electrical connections and mechanical support while minimizing package size and cost.
Innovation Solution
A semiconductor package structure with a connecting element, such as a silicon bridge, disposed in the interposer substrate, enabling fine pitch electrical connections and maintaining interposer substrate routability and bump density, while reducing the need for through silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures are used, then manufacturing simplicity is maintained, but electrical connection efficiency and mechanical support are inadequate
Solution Approach 1:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical packaging by stacking semiconductor dies vertically and connecting them through the substrate. This dimensional change enables efficient electrical connections between multiple dies while maintaining a compact footprint, resolving the contradiction between connection efficiency and structural complexity.
Solution Approach 2:
The substrate serves as an intermediary element that provides mechanical support and electrical interconnection between multiple semiconductor dies. By introducing this intermediate component, the patent achieves reliable electrical connections and mechanical stability without requiring complex direct die-to-die bonding structures.
2Volume of moving object
If package size is reduced, then miniaturization is achieved, but mechanical support and electrical connections become insufficient
Solution Approach 1:
The patent achieves miniaturization by stacking components vertically in three dimensions rather than expanding horizontally. This vertical integration reduces the package footprint and volume while maintaining adequate mechanical support through the substrate structure that spans the entire package area.
Solution Approach 2:
The substrate performs multiple functions simultaneously: it provides mechanical support for all stacked dies, establishes electrical interconnections between layers, and serves as a mounting platform for external connections. This multi-functionality enables miniaturization without sacrificing mechanical strength.
3Reliability
If through silicon vias are used for connections, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The substrate acts as an intermediary that provides electrical interconnection between stacked dies without requiring through-silicon-vias in each die. This approach simplifies manufacturing by eliminating the complex TSV formation process while maintaining reliable electrical connectivity through the substrate's conductive pathways.
Solution Approach 2:
The patent extracts the electrical interconnection function from the semiconductor dies themselves and relocates it to the substrate. By removing the requirement for TSVs in the dies and providing connections through the substrate instead, the manufacturing process is significantly simplified while electrical connectivity is preserved.
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a connecting element, a first semiconductor device, a second semiconductor device, a first underfill layer, and a package layer. The interposer substrate is disposed on the carrier substrate. The connecting element is disposed in the interposer substrate. The connecting element includes a dielectric element and first conductive features disposed in the dielectric element. The first semiconductor device and the second semiconductor device are disposed on the interposer substrate. The first semiconductor device is electrically connected to the second semiconductor device through the connecting element. The first underfill layer is disposed between the first semiconductor device, the second semiconductor device, and the interposer substrate. The package layer surrounds the first semiconductor device, the second semiconductor device, and the first underfill layer.