Interposer SiP Layout for Shorter Multi-Chip Signal Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing functionality and shrinking features of modern integrated circuits result in longer and thinner interconnections between ICs, leading to increased signal transmission times, which can be addressed by packaging multiple ICs together using an interposer substrate to reduce wire distances and improve electrical signal speed.
Innovation Solution
A system-in-package (SiP) structure is developed, utilizing an interposer substrate with through-semiconductor vias (TSVs) and redistribution layers to connect multiple ICs, including semiconductor die mounted in a flip-chip orientation, encapsulated in a molding material, and singulated to form individual units with reduced interconnect lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ICs are mounted on a printed circuit board with wire bonds, then the system can achieve multiple integrated circuit functions, but the wire bond distances become long leading to increased signal transmission times
Solution Approach 1:
Multiple ICs are combined into a single package structure where they are mounted on an interposer substrate, eliminating the need for long wire bonds between separate ICs on a PCB. The ICs are positioned in close proximity, reducing interconnection distances and improving signal transmission speed.
Solution Approach 2:
An interposer substrate is introduced as an intermediary component between multiple ICs. This interposer provides a common mounting platform with integrated interconnection structures (such as TSVs and redistribution layers) that enable short-distance electrical connections between ICs, replacing the long wire bonds that would otherwise be needed.
2Speed
If multiple ICs are combined inside a single package, then signal transmission distance is reduced, but the device structure becomes more complex
Solution Approach 1:
The complex interconnection function is segmented into modular components: the interposer substrate, TSV structures, redistribution layers, and IC mounting areas. This segmentation allows each component to be optimized independently while working together to achieve short interconnect lengths and high signal speed.
Solution Approach 2:
The interposer substrate utilizes three-dimensional interconnection structures, particularly through-silicon vias (TSVs), to establish vertical electrical connections. This dimensional approach allows signals to travel through the thickness of the interposer rather than along its surface, effectively reducing interconnect length in a compact volume.
3Productivity
If wafer-level processing is used to manufacture the interposer substrate, then manufacturing efficiency is improved, but precise alignment and integration of multiple die become more challenging
Solution Approach 1:
The interposer substrate is prepared in advance with pre-formed TSV structures, redistribution layers, and alignment features before the ICs are mounted. This preliminary preparation of the interposer enables precise alignment during the subsequent die bonding process, even when using efficient wafer-level processing methods.
Solution Approach 2:
Wafer-level processing techniques are used to manufacture the interposer substrate, replacing traditional discrete component assembly methods. This includes wafer-level TSV formation, wafer-level redistribution layer deposition, and wafer-level die bonding, which collectively improve manufacturing efficiency while maintaining precision through process integration.
Data Source
AI summary
A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.