Interposer SiP Layout With TSVs for Faster Chip-to-Chip Signaling
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Solution Overview
Problem
The increasing functionality and shrinking features of modern integrated circuits result in longer and thinner interconnections between ICs, leading to increased signal transmission times.
Innovation Solution
A system-in-package (SiP) structure is developed, combining multiple ICs on an interposer substrate with through-silicon vias (TSVs) to create shorter wire distances and wider conduits for electrical signals, using a redistribution layer (RDL) and flip-chip orientation for improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ICs are mounted on a printed circuit board with wire bonds, then the system can achieve basic connectivity, but the signal transmission distance becomes long and transmission time increases
Solution Approach 1:
Multiple ICs are combined into a single package structure, integrating previously separate components (ICs, interposer, TSVs, RDLs) into one unified system. This merging eliminates the need for external wire bonds and reduces overall signal path length, directly improving transmission speed while reducing interconnection length.
Solution Approach 2:
The patent transitions from planar PCB mounting to three-dimensional vertical stacking using TSVs that penetrate through the interposer substrate. This dimensional change allows signals to travel vertically through the package rather than laterally across the PCB, significantly reducing transmission distance and improving speed.
2Speed
If ICs are combined in a system-in-package, then signal transmission distance is reduced, but manufacturing complexity increases
Solution Approach 1:
The interposer substrate is prepared in advance with pre-formed TSVs and RDLs before IC mounting. This preliminary preparation of the interconnection infrastructure simplifies the overall assembly process by establishing the signal pathways beforehand, reducing the complexity of on-site interconnection work.
Solution Approach 2:
The interposer substrate acts as an intermediary component between multiple ICs, providing a standardized interface and simplifying the integration process. Rather than directly connecting ICs to each other, the interposer mediates all inter-IC connections, reducing manufacturing complexity by standardizing the interface requirements.
3Speed
If through-silicon vias are used to create shorter interconnections, then signal speed improves, but manufacturing precision requirements increase
Solution Approach 1:
TSVs are nested within the interposer substrate structure, with conductive material embedded inside the silicon matrix. This nested configuration allows precise via formation through controlled depth etching and fill processes, maintaining alignment precision while achieving the short interconnection lengths needed for high-speed signaling.
Data Source
AI summary
A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.