Interposer Solder Fillet Limiting Layers for Warpage Stress
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Solution Overview
Problem
Electronic components mounted on printed circuit boards (PCBs) are prone to mechanical defects and property degradation due to warpage, especially in vehicles where high mechanical reliability is required, as the reduced thickness of components makes them susceptible to stress and curvature.
Innovation Solution
The electronic component design includes a multilayer capacitor with dielectric layers and internal electrodes, paired with an interposer having solder fillet limiting layers made of organic material, which are connected via high-melting-point solder and plated with nickel and tin layers, reducing warpage stress by absorbing vibrations and preventing direct transmission of board warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of electronic component is reduced, then the electronic device thickness is reduced, but the electronic component becomes susceptible to warpage stress and mechanical defects
Solution Approach 1:
The patent applies beforehand cushioning by introducing a damping material layer between the electronic component and the printed circuit board before assembly. This damping layer is positioned in advance to absorb and mitigate warpage stress before it can reach the thinned electronic component, thereby protecting it from mechanical defects while maintaining the reduced thickness design
Solution Approach 2:
The patent uses an intermediary approach by inserting a damping material layer as a mediator between the printed circuit board and the electronic component. This intermediate layer acts as a stress buffer that decouples the warpage stress from the electronic component, allowing the component to maintain its thin profile while the intermediary absorbs the mechanical stress
2Reliability
If solder fillet limiting layers are added to external terminals, then warpage strength is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies merging by integrating the solder fillet limiting layers directly into the external terminals of the interposer during the same manufacturing process. Instead of adding separate components, the limiting layers are formed as part of the terminal structure itself, thereby enhancing warpage strength while minimizing additional manufacturing complexity
Solution Approach 2:
The patent uses parameter changes by modifying the physical and chemical properties of the external terminals through the addition of solder fillet limiting layers. These layers change the stress distribution parameters at the terminal surfaces, enhancing warpage resistance by controlling solder flow and stress concentration points during the soldering process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the warpage strength of the electronic component, preventing cracks and property degradation while reducing acoustic noise by absorbing vibrations and isolating the component from board warpage stress, even with a smaller interposer size.
Implementation Method 1
reducing acoustic noise by absorbing vibrations
Implementation Method 2
isolating the component from board warpage stress
Data Source
AI summary
An electronic component includes a multilayer capacitor including a capacitor body having first to sixth surfaces, and first and second external electrodes; and an interposer including an interposer body and first and second external terminals; and the capacitor body includes a plurality of dielectric layers and a plurality of first and second internal electrodes, the first and second internal electrodes are exposed through the third and fourth surfaces of the capacitor body, respectively, and the interposer further includes first and second solder fillet limiting layers disposed on upper sides of both surfaces of each of the first and second external terminals in the first direction, respectively.