Interposer Stabilization Layer for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Interposers used in semiconductor structures tend to warp during package assembly due to differences in thermal expansion coefficients between the silicon body and metal routing layers, leading to improper solder ball connections and potential short circuits.
Innovation Solution
A stabilization layer is formed on the back side of the interposer to counteract stresses from thermal expansion of the wiring layers, and a carrier frame is used to provide additional support during reflow, preventing warpage and ensuring proper alignment and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal routing layers are added on the interposer to connect TSVs to contacts, then electrical connectivity is improved, but thermal expansion differences cause warpage during reflow
Solution Approach 1:
The patent modifies the physical and chemical parameters of the interposer structure by adding a stabilization layer with specific material properties (different coefficient of thermal expansion) to counterbalance the thermal expansion of metal routing layers, thereby maintaining interposer flatness during temperature cycles while preserving electrical connectivity
Solution Approach 2:
The patent creates a composite structure by combining the silicon interposer body, metal routing layers, and a stabilization layer made of different materials (such as epoxy or polymer) to achieve both electrical functionality and dimensional stability through the composite's balanced thermal expansion characteristics
2Ease of manufacture
If the interposer is thinned to less than 100 microns to form TSVs, then via formation is improved, but structural rigidity decreases leading to increased warpage susceptibility
Solution Approach 1:
The patent changes the structural parameters of the interposer by introducing a stabilization layer that compensates for the reduced rigidity of thinned silicon, allowing TSV formation in thin substrates while maintaining sufficient mechanical strength to resist warpage during assembly and reflow processes
3Reliability
If wiring is concentrated on the periphery of the interposer for routing, then connectivity is improved, but uneven thermal expansion increases warpage tendency
Solution Approach 1:
The patent applies a counterbalancing approach by placing a stabilization layer on the opposite side of the interposer from the concentrated peripheral wiring, creating a counterweight effect that offsets the uneven thermal expansion stresses and prevents warpage while maintaining the necessary connectivity routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stabilization layer effectively reduces warpage and ensures reliable solder ball connections, preventing short circuits and ensuring uniform thermal expansion, while the carrier frame provides rigidity to maintain interposer flatness during assembly.
Implementation Method 1
Due to differences in the coefficients of thermal expansion of the silicon body and the metal routing layer, as well as to film stresses generated during silicon layer processing, interposers have a tendency to warp during package assembly
Implementation Method 2
Once aligned, the solder bumps are heated to reflow the solder bumps and electrically connect contacts of the first contact array with the contact pad of the matching contact array
Implementation Method 3
The underfill then flows into the narrow gap due to capillary action and spreads between the die and the substrate until the gap between the die and substrate has been filled
Data Source
AI summary
In one embodiment, an interposer resistant to warping is provided. The interposer includes a semiconductor body having a first contact array included on a first side of the semiconductor body. Vias are formed through the semiconductor body. One or more wiring layers are included on the first side of the semiconductor body. The wiring layers electrically couple each contact of the first contact array to a respective one of the vias. Contacts of a second contact array, included on a second side of the semiconductor body, are respectively coupled to the vias. A stabilization layer is included on the second side of the semiconductor body. The stabilization layer is configured to counteract stresses exerted on a front side of the interposer due to thermal expansion of wiring layers.