Interposer-Based Stacked Chip Package Structure
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Solution Overview
Problem
Current three-dimensional integrated circuit packaging technologies face challenges in reducing size and improving density, particularly in manufacturing processes for stacked packaging schemes like package-on-package (PoP) configurations, which require efficient electrical connections and mechanical support without damaging the semiconductor dies.
Innovation Solution
A chip package structure is developed, comprising a semiconductor die surrounded by a dielectric structure with conductive structures penetrating through, an interposer substrate bonded over the first package, and a second package electrically coupled through conductive features, allowing for reliable electrical connections and mechanical support between stacked packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If stacked packaging schemes like package-on-package are used to reduce size and improve density, then the volume and integration density are improved, but the manufacturing complexity and difficulty of achieving reliable electrical connections increase
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the first and second packages. The interposer substrate includes conductive features that electrically couple the conductive structures from the first package to the second package, simplifying the manufacturing process by providing a stable platform for electrical connections rather than attempting to directly connect the stacked packages
Solution Approach 2:
The package structure is segmented into distinct functional components: the first package with its semiconductor die and conductive structures, the interposer substrate with conductive features, and the second package. This segmentation allows each component to be manufactured and prepared separately, then assembled together, reducing overall manufacturing complexity
2Reliability
If conductive structures penetrate through dielectric structure to provide electrical connections, then electrical connectivity is achieved, but the risk of damaging semiconductor dies during manufacturing increases
Solution Approach 1:
The dielectric structure serves as a cushioning or protective layer surrounding the semiconductor die. The conductive structures penetrate through this dielectric structure at controlled locations, and the dielectric material provides mechanical support and protection during the penetration process, reducing the risk of damage to the fragile semiconductor die
Solution Approach 2:
The dielectric structure is formed around the semiconductor die before the conductive structures are created. This preliminary formation of the dielectric structure establishes a protective environment and defined pathways for the conductive structures, ensuring that subsequent penetration processes do not inadvertently damage the die
Data Source
AI summary
A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.