Interposer-Stacked Semiconductor Package for Compact Multi-Chip Integration
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Solution Overview
Problem
There is a demand for semiconductor packages that can accommodate multiple semiconductor chips in a compact and efficient manner, particularly in electronic devices that require increased functionality and reduced size, while effectively managing heat dissipation and electrical connections.
Innovation Solution
A semiconductor package design featuring a package substrate with distinct mounting regions for multiple semiconductor chips, an interposer substrate, and conductive connectors, which allows for the stacking and lateral spacing of chips to optimize heat dissipation and electrical connectivity, including the use of passive devices and external connection terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on one package substrate, then the functionality and capacity of electronic devices are improved, but the package size and complexity increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration using an interposer substrate. Multiple chips are arranged at different vertical levels (first chip on package substrate, second chip on interposer substrate, third chip on interposer substrate), enabling increased functionality within a compact footprint by utilizing the vertical dimension for chip integration.
2Productivity
If an interposer substrate is used to stack semiconductor chips, then the integration density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the chip integration system into distinct functional segments: a package substrate for mounting the first chip, an interposer substrate for stacking the second and third chips, and separate mounting regions for different chip types. This segmentation allows each substrate to be optimized independently for its specific function, simplifying the overall manufacturing process despite the three-dimensional configuration.
3Temperature
If conductive connectors are laterally spaced apart from semiconductor chips, then heat dissipation is improved, but the electrical connection complexity increases
Solution Approach 1:
The patent introduces conductive connectors as intermediary elements that laterally extend from the interposer substrate toward the chips without directly contacting them. These connectors are laterally spaced apart from the chip bodies, creating thermal pathways for heat dissipation while maintaining electrical connectivity through the interposer substrate's conductive structure, thus separating thermal management from direct electrical contact.
Data Source
AI summary
A semiconductor package includes a package substrate with first and second mounting regions at a top surface of the package substrate, a first semiconductor chip disposed on the first mounting region, a second semiconductor chip disposed on the second mounting region, an interposer substrate disposed on the second mounting region and covering the second semiconductor chip, a plurality of conductive connectors extending from a bottom surface of the interposer substrate to the top surface of the package substrate and laterally spaced apart from the second semiconductor chip, and a third semiconductor chip on a top surface of the interposer substrate. A first distance between a top surface of the first semiconductor chip and the top surface of the package substrate is greater than a second distance between the top surface of the interposer substrate and the top surface of the package substrate.