Interposer Stacked Structure Spacing for Warpage Control
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with enhanced functionality and miniaturization poses challenges in achieving high memory bandwidth, as existing technologies struggle to provide structural reliability and efficient connection reliability in semiconductor packages.
Innovation Solution
A semiconductor package design incorporating a silicon interposer with through-electrodes, a stacked structure of semiconductor chips, and a package molding layer, where the stacked structure is spaced apart from the edges of the interposer, and the package molding layer forms a molding interface with the chip molding layer to minimize warpage and ensure structural and connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the stacked structure is positioned close to the edges of the interposer to maximize space utilization, then the area for mounting semiconductor chips is increased, but warpage occurs around the interposer compromising structural reliability
Solution Approach 1:
The patent applies local quality by creating different zones on the interposer surface: a first region where the stacked structure is positioned at a specific distance from edges to prevent warpage, and a second region where individual semiconductor chips are mounted adjacent to the stacked structure. This spatial differentiation resolves the contradiction by optimizing chip placement areas while maintaining structural integrity through controlled positioning away from edge-induced warpage zones.
2Productivity
If the stacked structure is positioned close to the edges of the interposer to increase integration density, then the number of mounted chips is increased, but connection reliability deteriorates due to warpage
Solution Approach 1:
The patent implements local quality by defining distinct functional regions: a first region for the stacked structure positioned at an optimized distance from interposer edges to minimize warpage impact, and a second region for individual chip mounting adjacent to the stacked structure. This regional differentiation enables high integration density while maintaining connection reliability by preventing warpage in the chip mounting zones.
3Strength
If the package molding layer is applied to cover the entire interposer surface to protect all components, then comprehensive protection is achieved, but warpage is exacerbated due to uneven thermal contraction
Solution Approach 1:
The patent applies local quality by positioning the stacked structure in a first region at a specific distance from the interposer edges, creating a buffer zone that prevents warpage propagation to the chip mounting areas. The package molding layer is then applied to cover the stacked structure and mounted chips, achieving comprehensive protection while the strategic positioning of the stacked structure prevents warpage-induced structural instability.
Data Source
AI summary
A semiconductor package includes an interposer including a base layer and a plurality of interposer through-electrodes penetrating the base layer; at least one stacked structure attached to the interposer and including a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and a chip molding layer on a side surface of the plurality of second semiconductor chips; a plurality of third semiconductor chips attached to the interposer adjacent the at least one stacked structure; and a package molding layer extending around the at least one stacked structure and the plurality of third semiconductor chips on the interposer.