Multi-Layer Interposer Stacking via Through-Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques for stacking leaded packaged integrated circuits face complexities in connecting non-adjacent leads, particularly in multi-layer interposer or carrier structures, which often require costly and error-prone buried vias and blind vias for complex routing, increasing costs and quality issues due to tight tolerances.
Innovation Solution
A system and method using multi-layer interposer or carrier structures with conductive transits like plated-through holes, along with selective connective pads and capture pads, to establish electrical connections between leads of integrated circuits, eliminating the need for buried and blind vias by implementing trace routing and other connective structures within the interposer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-layer interposer structures with buried vias and blind vias are used to connect non-adjacent leads, then complex routing requirements are met, but manufacturing cost increases and quality issues arise due to tight tolerances
Solution Approach 1:
The patent divides the interposer structure into multiple layers with through-vias connecting them, replacing the complex buried and blind via system. This segmentation allows each layer to be manufactured independently with standard via processes, avoiding the tight tolerances required for buried and blind vias while maintaining the ability to route signals between non-adjacent leads through the stacked layers.
Solution Approach 2:
The patent adds a vertical dimension by stacking multiple interposer layers with through-vias, transforming the complex 2D routing problem into a 3D solution. Signals can travel vertically through through-vias between layers and horizontally within layers, providing multiple routing paths without requiring complex buried or blind via structures, thereby simplifying manufacturing while achieving complex connectivity.
2Adaptability or versatility
If multi-layer interposer structures with buried vias and blind vias are used for complex routing, then non-adjacent lead connections are achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the via structure into through-vias that span multiple layers, replacing the complex combination of buried vias (embedded within layers) and blind vias (terminated within layers). This segmentation simplifies manufacturing by using standard through-via processes that are less complex and costly than buried and blind via fabrication, while still achieving connections between non-adjacent leads through the vertical stacking approach.
Solution Approach 2:
The through-vias serve multiple functions: they provide electrical connections between layers, act as structural support elements, and enable routing flexibility. This multi-functionality reduces the need for specialized buried and blind via structures, simplifying the overall manufacturing process while maintaining the capability to connect non-adjacent leads.
3Manufacturing precision
If tight tolerances are used for buried vias and blind vias to achieve complex routing, then connection precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses through-vias that extend completely through each layer, allowing for larger, more tolerant via dimensions compared to buried and blind vias. This segmentation approach maintains connection precision by providing clear entry and exit points for plating and alignment, while reducing manufacturing cost by eliminating the tight tolerance requirements associated with partial-depth via formation processes.
Data Source
AI summary
The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.