Interposer Substrate Layout for Fine-Pitch Semiconductor Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor packaging field faces challenges in achieving high-performance semiconductor chips with fine bump pitches on large-area package substrates, requiring efficient wiring formation while maintaining low manufacturing costs and high yield.
Innovation Solution
A method involving the formation of lower and upper redistribution structures on carriers, with specific pad widths and connection bumps, is used to create an interposer substrate that connects semiconductor chips to a base substrate with fine pitch wiring, allowing for efficient electrical connections and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine bump pitch wiring is formed on large-area package substrate, then semiconductor chip performance is improved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent divides the wiring formation process into multiple stages using different carriers. First, lower redistribution patterns are formed on a first carrier with relaxed pitch requirements. Then, an interposer substrate is introduced to bridge between the coarse lower wiring and fine upper wiring. This segmentation allows each stage to be optimized independently, achieving fine pitch wiring without proportionally increasing manufacturing difficulty.
Solution Approach 2:
The interposer substrate serves as an intermediary component between the base substrate and semiconductor chips. It contains both lower connection pads (matching coarse pitch) and upper connection pads (matching fine pitch), enabling transition between different pitch requirements. This intermediary structure resolves the contradiction by providing a buffer that decouples the manufacturing constraints of fine pitch wiring from the large-area substrate requirements.
2Manufacturing precision
If fine bump pitch wiring is formed on large-area package substrate, then semiconductor chip performance is improved, but manufacturing yield decreases
Solution Approach 1:
By segmenting the wiring formation into multiple carriers and stages, the patent reduces the complexity of any single manufacturing step. Each carrier can be processed and validated independently before assembly, allowing defects to be detected and corrected at intermediate stages rather than discovering failures only after complete assembly. This improves overall manufacturing yield.
Solution Approach 2:
The interposer substrate provides a buffer zone that cushions against manufacturing variations. The lower connection pads on the interposer are designed with larger dimensions and greater spacing, providing a tolerance margin that accommodates variations in bump placement and wiring alignment. This beforehand cushioning prevents minor manufacturing deviations from causing complete connection failures, thereby improving yield.
3Strength
If connection pads have larger width for reliability, then connection strength is improved, but wiring density decreases
Solution Approach 1:
The patent applies different pad width specifications at different locations and levels. Lower connection pads (connecting to base substrate) have larger widths for mechanical strength and reliability. Upper connection pads (connecting to semiconductor chips) have smaller widths optimized for fine pitch wiring density. This local differentiation allows each connection interface to be optimized for its specific requirements without compromising overall system performance.
Solution Approach 2:
The patent resolves the area conflict by transitioning to a three-dimensional stacked architecture. Multiple layers of redistribution patterns are formed on different carriers (base substrate, interposer, chip) at different vertical positions. This vertical stacking allows larger lower pads and smaller upper pads to coexist without competing for the same planar area, effectively decoupling the trade-off between connection strength and wiring density through dimensional transformation.
Data Source
AI summary
A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.