Interposer Packaging Substrate with Stress Releasing Gap
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Solution Overview
Problem
Existing packaging substrates face reliability issues due to thermal stress from differences in thermal expansion coefficients between the substrate and semiconductor chips, and they cannot accommodate high wiring density due to inadequate pad spacing.
Innovation Solution
A packaging substrate with a multilayered interconnect board, an insulation supporting layer, an interposer, a compliant layer, and a redistribution layer, featuring a stress releasing gap and conductive posts to buffer thermal expansion differences, along with a compliant layer made of materials like polyimide or silica gel, and an interposer made of silicone or glass, to ensure reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If low-k dielectric material is used to enhance electrical performance, then signal integrity is improved, but thermal stress resistance deteriorates due to large difference of thermal expansion coefficients
Solution Approach 1:
The patent introduces a compliant layer as an intermediary between the packaging substrate and the semiconductor chip. This compliant layer has intermediate thermal expansion properties that bridge the gap between the low-k dielectric substrate and the chip, absorbing thermal stress and preventing fracture while allowing the low-k material to maintain its electrical performance benefits.
Solution Approach 2:
The patent creates a composite structure by combining the low-k dielectric packaging substrate with a compliant layer made of different materials. This composite approach allows each layer to contribute its specific properties: the low-k substrate provides electrical performance while the compliant layer provides thermal stress resistance, achieving both goals simultaneously.
2Reliability
If pad size is increased to ensure reliable solder connections, then connection reliability is improved, but wiring density deteriorates due to larger interval between pads
Solution Approach 1:
The interposer acts as an intermediary component with its own pad structure that can be independently optimized. The interposer provides larger pads for reliable solder connections while maintaining smaller pitch dimensions, effectively decoupling the pad size requirement from the wiring density requirement and allowing both to be optimized simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates thermal stress and maintains reliable electrical connections by buffering thermal expansion differences, enhancing product reliability and accommodating high wiring densities.
Implementation Method 1
both the stress releasing gap and the compliant layer of the present invention can buffer a difference of thermal expansion coefficients between the interposer and its surrounding components so as to improve product reliability
Implementation Method 2
The conductive posts penetrate the compliant layer and electrically connect with the multilayered interconnect board
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A packaging substrate (100) including following elements is provided. The insulation supporting layer (120) is disposed on a first surface (112) of the multilayered interconnect board (110) and has an opening region (R10). A portion of the first surface (112) is exposed at the opening region (R10). The interposer (130) is disposed on the first surface (112) at the opening region (R10). A third surface (130A) of the interposer (130) faces the first surface (112) of the multilayered interconnect board (110). A stress releasing gap (136) is between an outer-sidewall of the interposer (130) and an inner-sidewall of the opening region (R10). The compliant layer (170) is disposed between the third surface (130A) and the first surface (112). The interposer (130) has through holes (132) and conductive posts (134) disposed in the through holes (132). The conductive posts (134) penetrate the compliant layer (170) and electrically connect with the multilayered interconnect board (110). The redistribution layer (140) is disposed on a fourth surface (130B) of the interposer (130) and is electrically connected with the conductive posts (134).