Interposer Support Structure to Prevent Semiconductor Package Warpage

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Solution Overview

Problem

The increasing demand for miniaturized, high-functionality semiconductor packages poses a challenge in preventing warpage of interposers, which is critical for maintaining product reliability and electrical connectivity between stacked semiconductor chips.

Innovation Solution

A semiconductor package design that includes a first substrate with a conductive pattern, a semiconductor chip, an interposer with a support member and conductive pattern, and a second substrate, where the interposer is spaced apart from the semiconductor chip and connected via a connection member to prevent warpage and ensure reliable electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the thickness of the interposer is reduced to enable miniaturization of the POP-type semiconductor package, then the package size is reduced, but the possibility of warpage of the interposer increases

Engineering Contradiction:
Improvepackage sizeVSAvoidinterposer warpage
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The interposer is segmented into multiple thin insulating layers stacked together, with conductive patterns formed in each layer. This segmentation allows the interposer to maintain mechanical stability and prevent warpage while achieving overall miniaturization of the package structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interposer employs composite material structure consisting of multiple insulating layers with different material properties. This composite construction provides both mechanical reinforcement to prevent warpage and enables the reduced thickness required for package miniaturization.

Inventive Principle:
Principle #40Composite materials

2Length of moving object

If the interposer is disposed close to the semiconductor chip to reduce package thickness, then the package is miniaturized, but the risk of interposer warpage increases

Engineering Contradiction:
Improvepackage thicknessVSAvoidinterposer stability
Core Design Contradiction:
Length of moving objectVSStability of the object's composition

Solution Approach 1:

The interposer is divided into multiple thin insulating layers (first insulating layer, second insulating layer, third insulating layer) stacked in sequence. This segmentation maintains structural stability even when the overall thickness is reduced, preventing warpage while enabling compact package design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of increasing thickness in the vertical dimension to prevent warpage, the solution adds structural complexity in the horizontal dimension by incorporating support members and optimizing the layout of conductive patterns across multiple layers, thereby maintaining stability without increasing package thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240096819A1Semiconductor package
Publication Date: 2024.03.21 SAMSUNG ELECTRONICS CO LTD
  • US20240096819A1 patent drawing
  • US20240096819A1 patent drawing
  • US20240096819A1 patent drawing

AI summary

There is provided a semiconductor package in which warpage of an interposer is prevented to improve product reliability. The semiconductor package comprising a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer, a semiconductor chip disposed on the first substrate, an interposer disposed on the semiconductor chip, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer, a support member disposed on a bottom surface of the second insulating layer and is in contact with an upper surface of the semiconductor chip, wherein the support member includes a first lower pad and a bump disposed under the first lower pad and a first connection member disposed between the first substrate and the interposer so as to connect the first conductive pattern and the second conductive pattern to each other.