Silicon Interposer Test Circuit for Stacked Die Access
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Solution Overview
Problem
Existing integrated circuit die stacks require separate testing of stacked die arrangements, which is inefficient and requires numerous connection points and continuity testing, complicating the testing process.
Innovation Solution
Incorporation of embedded test circuitry and IEEE 1149.1 Test Access Port (TAP) circuitry within a silicon interposer to facilitate testing of die stacks, reducing the need for separate testers and minimizing connection points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate testing of stacked die arrangements is performed, then testing can be conducted using conventional methods, but the number of connection points and continuity testing requirements increase
Solution Approach 1:
The patent merges the test circuitry with the interposer structure by integrating TAP controller and TAP port circuitry directly into the interposer. This consolidation eliminates the need for separate testing arrangements and reduces the number of external connection points required, while maintaining reliable testing capability through the unified structure.
2Reliability
If separate testers are used for each die in the stack, then individual die testing is achieved, but the testing process becomes more complex and time-consuming
Solution Approach 1:
The interposer is designed with universal test circuitry that can test multiple die in the stack simultaneously through a single TAP port. The TAP controller enables multi-functional testing operations including stimulus generation, response collection, and continuity testing across all die levels, eliminating the need for separate testers for each die and significantly reducing total testing time.
3Adaptability or versatility
If numerous connection points are used for testing, then comprehensive testing access is provided, but the interposer structure becomes more complex
Solution Approach 1:
The TAP port circuitry embedded in the interposer acts as an intermediary that provides comprehensive testing access to all die in the stack through a minimized set of external connection points. This intermediary structure translates external test signals into internal test operations, maintaining full testing versatility while simplifying the external interface and reducing structural complexity.
Data Source
AI summary
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.