Interposer Chip Test Pattern for Pre-Connection Verification
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Solution Overview
Problem
Current methods for connecting semiconductor chips of different sizes using interposer chips require testing of conductive patterns after connection, leading to scrapping of both defective and functional chips when defects are found.
Innovation Solution
An interposer chip with a substrate, upper and lower terminals, and conductive patterns, where a test pattern connects the patterns and can be cut after testing, allowing for pre-connection testing without affecting the semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive patterns are tested after connecting to semiconductor chips, then electrical characteristics can be verified, but both defective and functional chips are scrapped when defects are found
Solution Approach 1:
The patent forms a test pattern that electrically connects the conductive patterns before the interposer chip is connected to the semiconductor chips. This preliminary testing allows verification of electrical characteristics in advance, so that when defects are detected, only the defective interposer chip needs to be scrapped rather than wasting both the interposer chip and the semiconductor chips.
2Adaptability or versatility
If interposer chip is used to connect semiconductor chips of different sizes, then electrical connection is enabled, but testing must be performed after connection which increases complexity
Solution Approach 1:
The test pattern is formed in advance during the manufacturing process, allowing electrical characteristics to be tested before the interposer chip is assembled with semiconductor chips. This eliminates the need for complex post-assembly testing procedures and simplifies the overall manufacturing process while maintaining the ability to connect chips of different sizes.
3Reliability
If conductive patterns are electrically isolated, then signal integrity is maintained, but testing becomes impossible until chip connection
Solution Approach 1:
The test pattern acts as an intermediary structure that temporarily electrically connects the otherwise isolated conductive patterns. This intermediary connection enables testing of electrical characteristics while the interposer chip is still separate from the semiconductor chips. After testing is complete, the test pattern is removed, restoring the electrical isolation and signal integrity of the original conductive patterns.
4Loss of substance
If test pattern is added to enable pre-connection testing, then chip waste is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The test pattern is formed during the manufacturing process using standard photolithography and etching techniques, integrating the testing capability into the existing fabrication workflow. Although an additional step is required, the process uses conventional manufacturing methods and can be performed automatically, minimizing the impact on manufacturing simplicity while enabling valuable pre-connection testing that reduces chip waste.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the testing of interposer chip conductive patterns before connection, preventing the scrapping of functional semiconductor chips and ensuring only defective interposer chips are replaced.
Implementation Method 1
a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals
Implementation Method 2
a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals
Implementation Method 3
forming a test pattern that electrically connects the first conductive pattern to the second conductive pattern; supplying a first current from the first conductive pattern through the test pattern to the second conductive pattern
Data Source
AI summary
An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.