Interposer Chip Test Pattern for Connection Verification
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Solution Overview
Problem
Conventional interposer chips lack a common pad, making it difficult to accurately identify electrical connections between conductive wires and conductive patterns, especially when connecting semiconductor chips of different sizes.
Innovation Solution
Incorporating a test pattern with test lines, one-way elements, and a common pad on an insulating substrate, allowing a test current to flow through the conductive patterns and identifying electrical connections between conductive wires and semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional interposer chips without a common pad are used, then the structure is simpler, but the electrical connection identification between conductive wires and conductive patterns becomes inaccurate
Solution Approach 1:
A common pad is introduced as an intermediary element between the conductive patterns and the tester. This common pad serves as a reference point that enables accurate measurement of electrical connections by providing a stable electrical reference against which the connectivity of individual conductive patterns can be tested, thereby resolving the measurement inaccuracy problem without fundamentally changing the interposer chip's core function
Solution Approach 2:
The common pad is pre-configured on the interposer chip before the actual electrical connection testing is performed. This preliminary structural preparation ensures that when testing is conducted, the reference point is already in place, allowing for immediate and accurate electrical connection identification without requiring additional setup steps
2Ease of manufacture
If semiconductor chips of different sizes are directly connected using conductive wires, then the connection process is simpler, but the connection becomes difficult due to wire length limits
Solution Approach 1:
The interposer chip acts as a mediator substrate between semiconductor chips of different sizes. By providing conductive patterns and a common pad on this intermediate substrate, the system enables electrical connections between chips that would otherwise be too far apart for direct wire bonding, effectively extending the reachable distance while maintaining manufacturing simplicity
Solution Approach 2:
The connection path is segmented into multiple stages: first from the smaller chip to the interposer chip's conductive patterns, then from the common pad to the larger chip. This segmentation allows each wire bond to be of manageable length while achieving overall long-distance connectivity between chips of different sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate identification of electrical connections between conductive wires and conductive patterns, facilitating the connection of semiconductor chips of varying sizes and allowing for rapid repair of disconnected wires.
Implementation Method 1
A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern
Data Source
AI summary
An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern.