Interposer Test Point Layout for Crack Detection in Chip Packaging
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Solution Overview
Problem
The challenge in the chip packaging process is to accurately and efficiently detect whether an interposer is fragmented or has cracks, which affects the quality of the packaged chip due to stress and poor bonding connections.
Innovation Solution
A chip testing structure with a series of test points on the interposer, where sub-connecting wires at different heights are connected sequentially, allowing for the detection of open or short-circuit connections to determine if the interposer is fragmented or cracked by measuring test potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interposer is packaged through an interposer with stress effect, then the chip packaging process can be completed, but the interposer may be fragmented or cracked causing poor quality
Solution Approach 1:
The patent applies preliminary action by implementing test points and test wiring layers before the final packaging process. The test structure includes test points embedded in the interposer and connected through multiple wiring layers, allowing detection of fragmentation or cracking to occur before the interposer is fully packaged. This enables early identification and removal of defective interposers, preventing quality issues in the final product.
2Difficulty of detecting and measuring
If test points are added to detect interposer fragmentation, then detection capability is improved, but the device structure becomes more complex
Solution Approach 1:
The patent merges the test structure with the existing interposer structure by integrating test points and test wiring layers into the interposer's wiring layers. The test points are embedded within the same wiring layers that carry functional signals, and the test wiring is combined with the interposer's existing interconnect structure. This integration approach enables fragmentation detection without adding separate, independent test structures, thereby reducing overall device complexity.
Solution Approach 2:
The test wiring layers serve multiple functions: they provide both functional interconnections for chip signals and test paths for detecting interposer fragmentation. The same wiring layers that carry operational signals also serve as test paths, allowing a single structure to fulfill both functional and diagnostic roles, thus reducing the need for additional dedicated test structures.
3Measurement precision
If multiple sub-connecting wires at different heights are used, then detection accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing test wiring across multiple wiring layers at different heights within the interposer. The test points are connected through vertical vias that pass through multiple wiring layers, creating a three-dimensional test path. This vertical arrangement allows detection of fragmentation at different depths and planes within the interposer, improving detection accuracy while utilizing the existing multi-layer wiring structure that is already part of the interposer fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables accurate and efficient detection of interposer fragmentation or cracking during the packaging process, ensuring the quality of the packaged chip by identifying potential issues early on.
Implementation Method 1
an electrical connecting wire of the plurality of the test points is provided in an interposer wiring layer of the interposer
Data Source
AI summary
A chip testing structure and a chip testing method are provided. The chip testing structure includes an interposer, a plurality of chips on the interposer, and a plurality of test points on the interposer. The plurality of the test points are connected in series, an electrical connecting wire of the plurality of the test points is provided in an interposer wiring layer of the interposer, and an electrical connecting wire of adjacent test potentials includes a plurality of sub-connecting wires, different sub-connecting wires are positioned at different heights of the interposer wiring layer, and the plurality of the sub-connecting wires are connected sequentially based on a height of the interposer wiring layer. When test potentials of the plurality of the test points indicate an open circuit connection, the interposer is indicated to be fragmented or have a crack.