Silicon Interposer Test Circuitry for Stacked Die Access
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Solution Overview
Problem
Existing silicon interposers lack integrated test circuitry, necessitating external testers for stacked die testing, which complicates the testing process and increases the number of connection points requiring continuity testing.
Innovation Solution
Incorporating IEEE 1149.1 Test Access Port (TAP) circuitry and embedded test circuitry within the silicon interposer, allowing for direct testing of stacked die through the interposer, reducing the need for external testers and minimizing connection points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external testers are used for stacked die testing, then testing coverage is achieved, but the number of connection points requiring continuity testing increases
Solution Approach 1:
The patent merges the external tester functionality with the interposer by integrating test circuitry directly into the interposer structure. This consolidation eliminates the need for separate external testing equipment and reduces the number of connection points by combining test and signal pathways through the same interposer infrastructure.
Solution Approach 2:
The interposer serves as an intermediary element that now includes built-in test circuitry. This intermediary structure mediates between the stacked dies and the external testing environment, providing both signal redistribution and testing functions through its integrated circuitry, thereby reducing the need for direct external connections to each die.
2Reliability
If external testers are used for stacked die testing, then testing functionality is provided, but the testing process becomes complicated
Solution Approach 1:
By merging test circuitry with the interposer structure, the patent simplifies the testing process into a single integrated operation. The interposer with embedded test circuitry allows testing to be performed through standard interposer interfaces, eliminating the need for complex external tester setups and multiple connection procedures.
3Difficulty of detecting and measuring
If more TSVs and connection points are used for testing, then testing access is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines testing access functions with existing interposer signal pathways. By integrating test circuitry that utilizes the same TSVs and connection structures as signal transmission, the design provides testing access without requiring additional manufacturing steps or separate test-specific infrastructure.
Data Source
AI summary
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.