Semiconductor Interposer Testing via Carrier Support
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Solution Overview
Problem
The existing methods for testing semiconductor structures with silicon interposers are time-consuming and costly due to the need for conductive pathways to pass through inner circuits of package substrates, leading to low throughput and increased fabrication costs, as good semiconductor chips and substrates are often discarded with defective interposers.
Innovation Solution
A method involving a carrier with insulation and supporting portions to support the semiconductor structure, allowing for pre-packaging electrical performance testing, which accelerates the testing process and enables replacement of defective interposers with good ones before packaging, thus reducing waste and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If testing is performed after the silicon interposer is disposed on the package substrate, then the electrical performance can be tested, but the testing process becomes time-consuming and throughput decreases
Solution Approach 1:
The patent applies preliminary action by performing electrical performance testing on the silicon interposer before it is mounted on the package substrate. The testing is conducted at an earlier stage when the interposer is still on the carrier, allowing defects to be identified before final assembly. This resolves the contradiction by enabling comprehensive electrical testing without requiring the interposer to be mounted on the substrate first, thereby maintaining high testing throughput while ensuring reliability.
2Reliability
If testing is performed after packaging, then complete electrical performance can be verified, but defective interposers cause good semiconductor chips to be discarded as junk
Solution Approach 1:
The patent performs electrical testing on the silicon interposer at an intermediate stage before final packaging assembly. By testing the interposer's electrical performance early in the manufacturing process, defective interposers can be identified and removed before good semiconductor chips are permanently attached. This preliminary testing action prevents the waste of functional chips that would otherwise be discarded along with defective interposers, while still ensuring complete electrical performance verification is achieved.
Solution Approach 2:
The patent segments the testing process into distinct stages: first testing the silicon interposer independently on the carrier, then subsequently testing the complete assembled structure. This segmentation allows the interposer to be evaluated separately before final assembly, enabling defective interposers to be identified and removed without affecting the fate of the semiconductor chips. The segmented approach resolves the contradiction by providing intermediate verification points that prevent unnecessary waste while maintaining comprehensive quality control.
3Reliability
If a conductive pathway through the package substrate is used for testing, then electrical performance can be tested, but the process becomes costly and time-consuming
Solution Approach 1:
The patent performs electrical testing on the silicon interposer at an intermediate manufacturing stage before final packaging assembly, rather than waiting until after complete packaging. By conducting the electrical performance test earlier in the process when the interposer is still accessible on the carrier, the testing can be performed more efficiently without requiring complex post-packaging access procedures. This preliminary testing action reduces both the time required and the complexity of the testing process while maintaining complete electrical performance verification.
Data Source
AI summary
A method of testing a semiconductor structure is provided, including providing at least a semiconductor structure having an interposer and a semiconductor element disposed on the interposer; disposing the semiconductor structure on a carrier having a supporting portion, with the interposer being supported by the supporting portion; and performing a test process. The semiconductor structure has been tested for its electrical performance prior to packaging, thereby eliminating the necessity for a conductive pathway to pass through an inner circuit of an package substrate. Therefore, the testing process is accelerated and the time is save.