Low-Conductivity Interposer for MCM Thermal Crosstalk Isolation
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Solution Overview
Problem
Next generation multi-chip-modules (MCMs) face challenges in thermal management due to unwanted thermal crosstalk between IC and EO components, necessitating efficient thermal insulation and electrical connectivity for high-speed/high-frequency signal transmission.
Innovation Solution
An electrically non-conductive interposer with low thermal conductivity is used between chips, made of materials like glass or fused silica, featuring RF waveguides and conductive traces for signal transmission, along with passive and active heat spreaders for temperature control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a common heat spreader is disposed on the topsides of the IC chip and the EO chip with the substrate disposed below, then heat dissipation is improved, but unwanted thermal crosstalk occurs between the chips
Solution Approach 1:
The patent divides the thermal management structure into separate components for each chip type. IC chips have dedicated heat spreaders that conduct heat away laterally, while EO chips are thermally isolated from the substrate. This segmentation allows each chip type to be managed thermally according to its specific requirements without interfering with the other, resolving the thermal crosstalk issue while maintaining effective heat dissipation.
Solution Approach 2:
The patent applies different thermal management approaches to different locations in the package. IC chips receive aggressive thermal management with heat spreaders and direct substrate attachment for maximum heat dissipation, while EO chips receive thermal isolation through elevated mounting and substrate openings to maintain their required operating temperature. This local differentiation resolves the contradiction by optimizing thermal management for each component's specific needs.
2Temperature
If the EO component is thermally insulated from the IC chip, then the specific operating temperature requirement is met, but electrical connectivity for high-speed signals must be maintained
Solution Approach 1:
The patent introduces an intermediate thermal barrier layer between the EO chip and substrate that selectively blocks thermal conduction while allowing electrical signals to pass through via conductive vias. This intermediary structure resolves the contradiction by providing thermal isolation to maintain the EO chip's operating temperature while preserving the electrical connectivity needed for high-speed signal transmission.
Solution Approach 2:
The patent separates thermal and electrical pathways into different dimensions. Thermal isolation is achieved through the vertical dimension with elevated mounting and substrate openings, while electrical connectivity is maintained through the horizontal dimension with conductive traces and vias in the interposer layer. This dimensional separation allows simultaneous achievement of thermal insulation and electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively isolates EO components thermally while maintaining high-speed electrical connections, reducing thermal crosstalk and ensuring precise temperature management for EO components.
Implementation Method 1
an interposer disposed on the substrate, wherein the interposer is electrically non-conductive and has a thermal conductivity (k) of k≥1E-6 W/cm-K and k≤1E-3 W/cm-K
Implementation Method 2
the interposer is electrically non-conductive and has a thermal conductivity (k) of k≥1E-6 W/cm-K and k≤1E-3 W/cm-K
Implementation Method 3
a heat spreader disposed on the EO component, wherein the heat spreader is in direct thermal contact with the EO component
Data Source
AI summary
A multi-chip-module includes, from a bottom to a top thereof, a substrate and an interposer disposed on the substrate. The interposer is electrically non-conductive and has a thermal conductivity (k) of k<20 W/(mK). A set of integrated circuit components or chips is disposed on the interposer. Each of a first subset of the set of the components or chips includes a passive heat spreader disposed on the chip. At least one chip of a second subset of the components or chips includes an active heat spreader disposed on the chip. The first and second sets of the components or chips have no components or chips in common. A common thermal interface is disposed on each passive heat spreader and each active heat spreader.