Interposer Thermal Via Layout for Semiconductor Package Cooling

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Solution Overview

Problem

Existing semiconductor package structures face challenges in thermal management as they struggle to efficiently dissipate heat generated during the operation of semiconductor dies, particularly in smaller devices that perform multiple functions, leading to potential damage from increased temperature.

Innovation Solution

The implementation of a semiconductor package structure that includes thermal vias disposed in an interposer or redistribution layer, which extend to the bottom surface and vertically overlap the semiconductor die, providing additional thermal dissipation paths by coupling with conductive structures and thermal interface materials to enhance heat transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If thermal management structures are added to semiconductor packages, then thermal dissipation efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvethermal dissipation efficiencyVSAvoidpackage structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The thermal via structure is nested within the interposer layer, which itself is part of the semiconductor package structure. The via extends through the interposer to reach the semiconductor die, creating a nested configuration where thermal management functionality is integrated within existing structural layers rather than adding separate external components.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The thermal via extends vertically through the interposer layer, utilizing the vertical dimension to create thermal conduction paths. This vertical extension allows heat to be conducted from the semiconductor die through the interposer to external heat sinks or dissipation structures, adding a vertical thermal management dimension to the otherwise planar package structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If thermal vias are extended to bottom surface of interposer, then heat transfer path is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveheat transfer efficiencyVSAvoidvia alignment precision
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The thermal via is formed within the interposer structure before final assembly with the semiconductor die. This preliminary formation allows the via to be precisely positioned and aligned with the die's thermal management requirements, ensuring proper thermal conduction paths are established before the die is mounted in its final position.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interposer acts as an intermediary structure that contains the thermal via, mediating between the semiconductor die and external thermal management systems. The interposer provides a stable platform for via formation and alignment, reducing the precision requirements on the final die-to-package alignment while ensuring proper thermal conduction through the via structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly improves thermal dissipation efficiency by creating multiple paths for heat transfer, effectively managing heat generated by semiconductor dies and preventing damage from high temperatures.

Implementation Method 1

The thermal via is disposed in the interposer and extends to a bottom surface of the interposer. The thermal via vertically overlaps the semiconductor die.

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240186209A1Semiconductor package structure
Publication Date: 2024.06.06 MEDIATEK INC
  • US20240186209A1 patent drawing
  • US20240186209A1 patent drawing
  • US20240186209A1 patent drawing

AI summary

A semiconductor package structure includes a substrate, a semiconductor die, a molding material, an interposer, and a thermal via. The substrate has a wiring structure. The semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. The molding material surrounds the semiconductor die. The interposer is disposed over the semiconductor die. The thermal via is disposed in the interposer and extends to a bottom surface of the interposer. The thermal via vertically overlaps the semiconductor die.