Interposer Through-Hole Formation for Reliable 3D Chip Packaging
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Solution Overview
Problem
The existing technologies for forming vias in interposer substrates are not mature, leading to challenges in improving the packaging yield and reliability of electronic devices.
Innovation Solution
A method involving forming a blind hole in a substrate, followed by the deposition of a protective layer and conductive elements, and then cutting to create a through hole, with a subsequent encapsulation process to enhance structural strength and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If three-dimensional packaging technology is used to stack chips, then the area occupied by chips is reduced, but the technology for forming quality vias in interposer substrates is not yet mature
Solution Approach 1:
The patent segments the via formation process into two distinct stages: first forming blind holes in the interposer substrate, then creating through holes after chip stacking. This segmentation allows each process to be optimized independently, avoiding the difficulty of forming high-quality vias through a single complex step while enabling 3D packaging.
2Strength
If blind holes are formed in the substrate before chip stacking, then the structural strength is improved, but an additional cutting step is required
Solution Approach 1:
The patent performs preliminary action by forming blind holes in the interposer substrate before stacking the chips. This preliminary via formation strengthens the substrate structure and allows for better process control. The additional cutting step is accepted as a necessary consequence of this preliminary action to achieve the desired via quality and structural integrity.
3Reliability
If through holes are formed after chip stacking, then the electrical performance is improved, but the process complexity increases
Solution Approach 1:
The patent segments the via formation into blind hole creation followed by through hole formation after chip stacking. This segmentation enables the through holes to be formed when the final device structure is established, improving electrical performance by allowing precise alignment and connection. The increased process complexity is managed by breaking down the formation into controllable sequential steps.
Data Source
AI summary
A method of manufacturing an electronic device is provided. The method includes the following steps: providing a substrate; forming a circuit structure on the substrate; forming a hole in the substrate; forming a conductive element in the hole; bonding a chip to the circuit structure; and performing a first cutting step to cut a portion of the circuit structure and the substrate, and forming a groove in the substrate.