Interposer with Through Vias for Semiconductor Package Signal Integrity
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently connecting multiple chips stacked on a substrate, leading to increased parasitic capacitance and reduced signal transmission speed due to direct electrical connections and complex wiring configurations.
Innovation Solution
A semiconductor package design that includes a package substrate, a lower chip connected via bonding wires, an interposer with through via electrodes, and an upper chip, allowing the upper chip to be electrically connected to the substrate through the interposer and lower chip without direct connections, thereby reducing parasitic capacitance and simplifying signal exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If direct electrical connections are made between the upper chip and the substrate, then signal transmission path is shortened, but parasitic capacitance increases and signal transmission speed decreases
Solution Approach 1:
An interposer is introduced as an intermediary component between the upper chip and the substrate. The interposer includes through via electrodes that provide electrical connection paths, allowing signals to be transmitted without direct contact between the upper chip and substrate, thereby reducing parasitic capacitance while maintaining signal transmission capability.
Solution Approach 2:
The electrical connection path is segmented into multiple sections: bonding wires connecting the lower chip to the substrate, through via electrodes in the interposer connecting the upper chip to the lower chip, and redistribution lines. This segmentation allows optimization of each section to minimize overall parasitic capacitance while maintaining signal integrity.
2Productivity
If multiple chips are stacked on a substrate with direct connections, then integration density is increased, but wiring complexity and parasitic capacitance increase
Solution Approach 1:
The interposer serves as a mediator that simplifies the wiring architecture by providing standardized connection interfaces. Through via electrodes vertically penetrate the interposer to connect upper and lower chips, eliminating the need for complex lateral wiring routes that would otherwise be required to achieve the same connections.
Solution Approach 2:
The connection architecture transitions from primarily lateral wiring on the substrate to vertical through via electrodes in the interposer. This dimensional change allows multiple chips to be stacked with simplified wiring, as connections are made through the thickness of the interposer rather than requiring complex planar routing.
3Reliability
If through via electrodes are used in the interposer, then electrical connection between chips is achieved, but manufacturing complexity increases
Solution Approach 1:
The interposer is prepared in advance with through via electrodes formed before chip mounting. This preliminary preparation allows the complex through via structure to be manufactured under controlled conditions, ensuring reliable electrical connections while separating the manufacturing complexity from the final assembly process.
Solution Approach 2:
The interposer acts as a pre-fabricated intermediary component that contains the through via electrodes. By preparing this intermediary element separately with all its complex internal connections, the overall manufacturing process is simplified - the interposer with pre-formed through vias can then be easily integrated with the chips in a single assembly step.
Data Source
AI summary
A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.