Interposer Trench Structure for Void-Free Semiconductor Packaging
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Solution Overview
Problem
The miniaturization of semiconductor packages, particularly in package-on-package (POP) configurations, leads to challenges in efficiently injecting molding materials due to narrowed spaces, resulting in voids within the molding layer, which reduces product reliability and can cause cracking in connection members during high-temperature processes.
Innovation Solution
Incorporating an interposer with a recessed trench and hole structure that secures additional space for molding material fluidity and allows void discharge through penetrating through portions, enhancing the reliability of the semiconductor package by preventing void formation and crack mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the space between the interposer and semiconductor chip is narrowed to achieve miniaturization, then the package size is reduced, but voids form in the molding layer due to insufficient space for material injection
Solution Approach 1:
The interposer bottom surface is segmented into a flat region and a recessed region, creating distinct zones that serve different functions: the flat region provides close spacing for miniaturization while the recessed region ensures adequate space for molding material injection, preventing void formation
Solution Approach 2:
Instead of uniformly increasing the spacing between interposer and chip, the invention introduces a recessed region that extends in the vertical dimension, providing additional space for material injection without increasing the horizontal footprint, thus maintaining miniaturization while preventing voids
2Reliability
If the spacing between interposer and semiconductor chip is increased to allow proper molding material injection, then void formation is prevented, but the package size increases
Solution Approach 1:
The recessed region is strategically positioned only where molding material injection is needed, rather than uniformly increasing spacing across the entire interposer-chip interface. This localized approach provides necessary injection space while maintaining close spacing in other areas, thus preventing voids without increasing overall package size
3Productivity
If high-temperature processes are applied to semiconductor packages, then manufacturing is completed, but cracks form in connection members due to voids in the molding layer
Solution Approach 1:
The recessed region is designed in advance to prevent void formation during molding material injection. By providing adequate space for complete material filling before high-temperature processes, the structure preemptively eliminates the root cause of subsequent cracking in connection members during thermal processing
Data Source
AI summary
A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer.