Interposer Package Layout for TSV Off-Landing and Leakage Control

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving smaller and more creative packaging techniques for semiconductor dies as the demand for shrinking electronic devices increases, necessitating improved integration density and reduced off-landing risk of conductive vias during processing.

Innovation Solution

The integration of an encapsulated interconnection die with through-substrate vias and a redistribution structure, featuring oversized conductive vias and isolation layers around the through-substrate vias, reduces the risk of electric leakage and enhances performance by maintaining structural integrity and connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density cannot be improved and off-landing risk increases

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging technique complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The interconnection die is divided into multiple package regions with different configurations, allowing each region to be optimized independently for specific functions while maintaining overall integration density improvements

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar packaging to three-dimensional stacking with multiple dies connected through through-substrate vias, enabling vertical integration and significantly improving integration density without increasing footprint area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If smaller through-substrate vias are used to increase density, then integration density improves, but off-landing risk increases

Engineering Contradiction:
Improvevia densityVSAvoidoff-landing risk
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

Different regions of the interconnection die have different via configurations - some areas use smaller high-density vias while other areas use larger viaS for reliable landings, allowing optimization of both density and reliability in different locations

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The redistribution structure acts as an intermediary between the through-substrate vias and the conductive vias, providing a transition layer that ensures reliable electrical connection even when via dimensions are reduced for higher density

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If conductive vias are made oversized to reduce off-landing risk, then reliability improves, but electric leakage risk increases

Engineering Contradiction:
Improveoff-landing risk reductionVSAvoidelectric leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The isolation layer extracts and removes the harmful effect of electric leakage by creating a dedicated insulating barrier that separates the oversized conductive via from the substrate, allowing the via to maintain its larger尺寸 for reliability without suffering from leakage problems

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250323126A1Integrated circuit packages and methods of forming the same
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250323126A1 patent drawing
  • US20250323126A1 patent drawing
  • US20250323126A1 patent drawing

AI summary

In an embodiment, a device includes: an interposer including: a back-side redistribution structure; an interconnection die over the back-side redistribution structure, the interconnection die including a substrate, a through-substrate via protruding from the substrate, and an isolation layer around the through-substrate via; a first encapsulant around the interconnection die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through-substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via that physically contacts the through-substrate via, the isolation layer separating the first conductive via from the substrate.