Interposer Substrate With Through-Silicon Vias and Mold Compound

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Solution Overview

Problem

Interposer substrates used in integrated circuit chip packaging are prone to warpage during the reflow process, leading to reduced yield and poor package reliability, and existing solutions fail to minimize the thickness of chip packages effectively.

Innovation Solution

A microelectronic package is designed with an interposer formed from a semiconductor substrate and through-silicon vias, where a mold compound is used to stiffen the package, replacing underfill material and allowing for closer placement of passive components, thus reducing thickness and preventing warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If an interposer substrate is used to reduce chip package thickness, then the thickness is reduced, but warpage occurs during reflow process

Engineering Contradiction:

Improvechip package thicknessVSAvoidpackage reliability

Core Design Contradiction:

Length of stationary objectVSReliability

Solution Approach 1:

The interposer substrate is segmented into multiple thinner layers (first interposer layer, second interposer layer) connected by through-silicon vias. This segmentation reduces the overall thickness while distributing thermal and mechanical stresses, preventing warpage during reflow process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structure combining silicon layers with copper interconnects and dielectric materials. This composite structure provides both mechanical strength to prevent warpage and electrical connectivity, achieving reliability while maintaining thin profile.

Inventive Principle:

Principle #40Composite materials

2Reliability

If underfill material is used to protect electrical connections, then connections are protected, but package footprint increases

Engineering Contradiction:

Improveelectrical connection protectionVSAvoidpackage footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the underfill material from the conventional placement and replaces it with mold compound that serves both as encapsulation and structural support. This eliminates the need for separate underfill layer, reducing footprint while maintaining connection protection.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The mold compound performs multiple functions: it encapsulates the IC chips, protects electrical connections, provides mechanical support, and enables closer placement of passive components. This multi-functionality replaces the specialized underfill material, reducing overall package area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10032696B2Chip package using interposer substrate with through-silicon vias

Publication Date: 2018.07.24 NVIDIA CORP

AI summary

A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon vias. A second redistribution layer is formed on a second side of the interposer, and is electrically coupled to the through-silicon vias. In some embodiments, a mold compound is connected to an edge surface of the interposer and is configured to stiffen the microelectronic package.