Semiconductor Package Layout Using Interposer TSVs and RDL
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration, miniaturization, and maintaining electrical reliability due to the use of multiple through-silicon vias, which can increase chip size and degrade production efficiency.
Innovation Solution
A semiconductor package design incorporating a package substrate, sub-packages with semiconductor chips, interposers, encapsulators, and redistribution layers, featuring through-silicon vias and horizontal wirings to enhance electrical connectivity and reduce chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple through-silicon vias are disposed in each semiconductor chip to achieve high integration, then electrical connectivity between chips is improved, but chip size increases and production efficiency degrades
Solution Approach 1:
The patent transitions from vertical through-silicon vias to a horizontal redistribution layer architecture. The redistribution layer is formed extending on the encapsulator and interposer, creating horizontal electrical connections instead of vertical ones. This dimensional change allows multiple connection points without increasing chip area, as the connections are distributed across the horizontal plane of the package substrate rather than penetrating through the chip thickness.
Solution Approach 2:
The patent introduces an interposer as an intermediary component between the semiconductor chip and the package substrate. The interposer includes through-silicon vias and a redistribution layer that provides electrical connection pathways. This intermediary structure absorbs the complexity of multiple connections, allowing the semiconductor chip itself to remain compact while achieving high integration through the mediating interposer layer.
2Adaptability or versatility
If multiple through-silicon vias are formed in each semiconductor chip, then electrical interconnection capability is enhanced, but manufacturing process complexity and production time increase
Solution Approach 1:
The patent segments the electrical interconnection function across multiple independent layers: the semiconductor chip, the encapsulator, the interposer with through-silicon vias, and the redistribution layer. This segmentation allows each layer to be manufactured and processed separately with optimized processes, rather than requiring multiple vias to be formed sequentially in the chip itself. The redistribution layer is formed as a separate structure extending on the encapsulator and interposer, enabling parallel processing and improved productivity.
Solution Approach 2:
The patent moves the complex via formation process from the vertical dimension (through-silicon vias in chip) to a horizontal dimension (redistribution layer extending on encapsulator and interposer). This dimensional shift allows the electrical interconnection capability to be achieved through planar layer formation and patterning processes, which are generally faster and more efficient than repeated via drilling and filling operations through the chip thickness.
Data Source
AI summary
A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.