Silicon Interposer TSV Architecture for Lower 3DIC Yield Loss
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density in two-dimensional integrated circuits due to physical constraints and increased complexity and yield loss when forming through-silicon vias after the formation of integrated circuits, which prolongs manufacturing cycle time.
Innovation Solution
A three-dimensional integrated circuit (3DIC) architecture using an interposer with through-substrate vias (TSVs) formed before bonding dies, eliminating the need for TSVs in device dies and allowing for reduced cycle time and yield loss by forming the interposer and TSVs concurrently with die formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are formed after the formation of integrated circuits, then connections between stacked dies can be achieved, but yield loss occurs and manufacturing cycle time is prolonged
Solution Approach 1:
The patent applies preliminary action by forming through-silicon vias (TSVs) in the interposer substrate before bonding the semiconductor dies. This allows the TSVs to be created during the substrate fabrication process rather than after die formation, enabling concurrent processing of substrates and dies. The TSVs are formed, filled with conductive material, and planarized in advance, so that when dies are bonded to the interposer, the interconnection structure is already in place, significantly reducing manufacturing cycle time and eliminating yield loss associated with post-die TSV formation.
2Quantity of substance
If more devices are integrated into one chip in two dimensions, then integration density improves, but circuit RC delay and power consumption increase due to increased number and length of interconnections
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration using an interposer substrate. Multiple semiconductor dies are bonded to the same interposer at different vertical levels, with through-silicon vias providing vertical interconnections. This vertical stacking approach dramatically increases the number of devices that can be integrated within a given footprint area, effectively increasing integration density without proportionally increasing interconnection length, as vertical TSV paths are more direct than lateral routing paths in 2D layouts.
3Reliability
If through-silicon vias (TSVs) are formed after the formation of integrated circuits, then interconnections between stacked dies can be established, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent merges the TSV formation process with the interposer substrate fabrication process. The through-silicon vias are formed, patterned, and filled with conductive material as integral steps in creating the interposer itself, rather than as separate post-die processes. This consolidation of processes reduces the total number of manufacturing steps, simplifies the overall manufacturing flow, and allows for better process integration and control, thereby reducing manufacturing process complexity while maintaining interconnection reliability.
Data Source
AI summary
A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.