Interposer UCIe Subchannel Routing for Signal Integrity

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Solution Overview

Problem

The challenge of routing high-speed, low-voltage UCIe channels through an interposer in 3DIC systems is complicated by long distances between dies, high data transfer rates, stringent timing and power requirements, and the absence of active devices, making it difficult to meet signal integrity and automated routing tool development.

Innovation Solution

The UCIe channels are partitioned into non-overlapping subchannels and routed separately, with distinct processes for signal and power/ground routing, allowing for automated planning and efficient use of routing area, and incorporating shielding to maintain signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed UCIe channels are routed through long distances in an interposer, then data transfer capability is improved, but signal integrity deteriorates due to timing and power requirements

Engineering Contradiction:
Improvedata transfer rateVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The interposer is divided into multiple routing regions with different interconnect types (first interconnects for certain signal groups, second interconnects for other signal groups). This segmentation allows optimization of routing paths for different signal characteristics, maintaining signal integrity while supporting high-speed data transfer across long distances.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different routing regions are assigned different interconnect structures and characteristics tailored to specific signal requirements. Certain signal groups receive specialized routing treatment (e.g., shielding, impedance control, length matching) appropriate to their speed and sensitivity characteristics, while other signals use different routing approaches.

Inventive Principle:
Principle #3Local quality

2Productivity

If automated routing tools are developed for UCIe channels, then routing efficiency is improved, but design complexity increases due to multiple constraints

Engineering Contradiction:
Improverouting efficiencyVSAvoidrouting constraint complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The routing process is segmented into multiple independent stages, with each stage handling specific signal groups and constraints. This allows automated tools to process routing in manageable chunks rather than attempting to solve all constraints simultaneously, improving computational efficiency while handling complex design requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Signal groups are pre-categorized and assigned to specific routing regions based on their characteristics before the actual routing process. This preliminary classification simplifies the automated routing task by pre-establishing routing constraints and regions, reducing the complexity of real-time decision-making in the routing tool.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If separate routing processes are used for signal and power/ground networks, then routing precision is improved, but processing time increases

Engineering Contradiction:
Improverouting precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The routing process is divided into separate stages for signal networks and power/ground networks, with each stage optimized for its specific requirements. Signal routing focuses on impedance control and length matching, while power/ground routing focuses on current capacity and voltage regulation, achieving high precision for each network type.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Power and ground networks are routed first to establish the electrical foundation and define available routing resources. This preliminary action allows subsequent signal routing to proceed more efficiently with pre-established reference planes and power delivery paths, reducing overall processing time while maintaining precision.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12517850B1Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels
Publication Date: 2026.01.06 SYNOPSYS INC
  • US12517850B1 patent drawing
  • US12517850B1 patent drawing
  • US12517850B1 patent drawing

AI summary

A description of an interconnect channel within an interposer (such as a Universal Chiplet Interconnect Express™ (UCIe) channel) includes first bump locations for a first interface to the interconnect channel on a first die, second bump locations for a second interface to the interconnect channel on a second die, and nets connecting corresponding first and second bump locations for the two interfaces on the two dies. A processing device partitions the interconnect channel into subchannels. The subchannels include corresponding clusters of first and second bump locations connected by nets. The bounding boxes for the subchannels are non-overlapping. For each subchannel, the nets within the subchannel are routed.