Interposer Upturned Mirror Structure for Wafer-Level PIC Testing
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Solution Overview
Problem
Existing methods for accessing optical signals in photonic integrated circuits (PICs) during fabrication are limited, hindering effective wafer-level testing and increasing processing costs.
Innovation Solution
The development of an upturned mirror structure on an interposer substrate allows optical signals to be routed into and out of planar waveguides, enabling wafer-level testing through the use of a probe head with both electrical and optical portions, facilitating evaluation of PIC performance before die separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fiber optic coupling methods are used to access optical signals in PICs, then the PIC can be tested after fabrication, but wafer-level testing during fabrication is not enabled and processing costs increase
Solution Approach 1:
The patent implements preliminary action by incorporating test waveguides and optical access structures (such as grating couplers or edge couplers) during the fabrication process itself. This allows the PIC to be tested at the wafer level before final packaging and fiber coupling, enabling performance evaluation to be completed during manufacturing rather than requiring post-fabrication testing with external fibers.
2Productivity
If wafer-level testing is implemented with proper optical access structures, then testing efficiency improves, but the device complexity increases due to additional waveguide and coupling structures
Solution Approach 1:
The patent applies universality by designing test waveguides and optical access structures that serve dual purposes: they enable wafer-level testing during fabrication while also functioning as part of the final device architecture. The same waveguide structures used for testing can be integrated into the functional circuitry, eliminating the need for separate dedicated test structures and reducing overall device complexity.
Solution Approach 2:
The patent extracts the testing function from the final device by creating dedicated test waveguides and optical access points that can be independently configured and removed or modified after testing. This allows the testing infrastructure to be separated from the functional components, enabling efficient wafer-level testing without permanently increasing the complexity of the operational device.
3Ease of manufacture
If optical access structures are added to enable wafer-level testing, then manufacturing costs decrease, but the manufacturing process becomes more complex with additional fabrication steps
Solution Approach 1:
The patent merges the testing infrastructure with the standard fabrication process by integrating test waveguides, grating couplers, and optical access structures into the same fabrication steps used for creating the functional PIC components. This combining approach allows wafer-level testing to be performed using existing manufacturing lines without requiring separate, complex fabrication processes, thereby reducing overall manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient wafer-level testing of PICs, reducing processing costs by allowing performance evaluation during fabrication and improving the reliability of PICs through functional testing.
Implementation Method 1
one or more upturned mirrors are formed in an interposer structure... the reflective surfaces of the mirrors intersect the pathways of optical signals propagating through the planar waveguides
Data Source
AI summary
A structure and method for the wafer level testing of interposer-based photonic integrated circuits is described that includes the formation of an upturned mirror structure and the method of utilizing the interposer-based mirror structure for electrical and optical testing of optoelectrical circuits that include emitting components such as lasers, detecting components such as photodetectors, and both emitting and detecting components. Electrical activation of the optoelectrical emitting or sending devices and the subsequent detection and measurement of the optical signals in detecting or receiving devices provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.