Interposer Via Coplanarity and Capacitor Integration
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Solution Overview
Problem
The increasing demand for high-performance semiconductor packages with improved signal and power integrity due to miniaturization and integration of semiconductor circuits requires advanced interposer structures that effectively connect multiple chips while maintaining high bandwidth and packaging efficiency.
Innovation Solution
A semiconductor package design incorporating an interposer substrate with a capacitor structure, multiple via layers, and a redistribution layer, where the vias and through vias penetrate through various insulating and etching stop layers to ensure electrical connectivity and signal integrity, with a simplified manufacturing process that forms coplanar surfaces for the vias and through vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are integrated in a compact package, then packaging efficiency and signal integrity are improved, but manufacturing complexity increases due to multiple via layers and etching stop layers
Solution Approach 1:
The interposer substrate is divided into multiple functional layers including first and second etching stop layers, first and second interlayer insulating layers, and multiple via structures (first vias, second vias, through vias). This segmentation allows each layer to serve specific functions in connecting multiple chips while maintaining manufacturing feasibility through standardized layering processes
Solution Approach 2:
The patent introduces vertical stacking of multiple via layers and etching stop layers to achieve three-dimensional interconnection. By transitioning from planar to vertical connectivity, the design enables compact multi-chip integration while managing signal paths through different depth levels, effectively utilizing the Z-dimension to reduce horizontal complexity
2Reliability
If via surfaces are formed at different planes, then electrical connectivity is achieved, but additional planarization processes are required increasing manufacturing steps
Solution Approach 1:
The patent merges the formation of first vias, second vias, and through vias into a single planarization process step. By coordinating the deposition and planarization operations to occur simultaneously or in tight sequence, multiple via structures achieve coplanar surfaces without requiring separate planarization steps for each via type, thereby reducing overall manufacturing complexity while ensuring reliable electrical connectivity
3Manufacturing precision
If etching stop layers are added for precise via formation, then via placement accuracy is improved, but the number of material layers and deposition steps increases
Solution Approach 1:
Etching stop layers are strategically positioned only at specific locations where via formation requires precise depth control. The first etching stop layer is located between the first and second interlayer insulating layers, while the second etching stop layer is positioned between the second interlayer insulating layer and the third etching stop layer. This localized application of etching stop layers provides necessary via placement accuracy only where critical, rather than uniformly across all layers
Data Source
AI summary
An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.