Interposer Via Bonding for Fine-Pitch Semiconductor Packaging
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable packages with high integration density while overcoming the difficulties in fabrication processes as feature sizes continue to decrease.
Innovation Solution
A package structure is formed by bonding conductive bumps directly to the end portions of conductive via structures within an interposer substrate, eliminating the need for conductive pads, which allows for self-aligned and fine-pitch joints, reducing the size and cost of the conductive bumps, and enabling high I/O throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive pads are used in the interposer substrate, then the bonding process is simplified, but the size and cost of conductive bumps increase
Solution Approach 1:
The patent removes the conductive pad layer from the interposer substrate, allowing conductive bumps to bond directly to the conductive via structures. This extraction of the intermediate pad layer reduces the required conductive bump size and material quantity while maintaining bonding functionality.
Solution Approach 2:
The conductive via structures are designed with segmented width profiles (narrower at the top, wider at the bottom), allowing the conductive bumps to bond directly to the exposed via ends without requiring large pad areas. This segmentation of the via structure enables direct bonding with smaller bumps.
2Productivity
If conventional packaging methods are used, then manufacturing processes are well-established, but integration density is limited
Solution Approach 1:
The patent transitions from planar bonding (requiring conductive pads on the surface) to vertical bonding (bonding directly to the ends of conductive via structures that protrude from the substrate). This dimensional change enables higher I/O throughput and integration density by utilizing the vertical dimension for electrical connections.
Solution Approach 2:
The conductive via structures are pre-formed with protruding ends before the bonding process. This preliminary preparation of the via structures eliminates the need for subsequent pad formation steps and enables direct bonding, simplifying the overall manufacturing process while achieving high integration density.
3Manufacturing precision
If feature sizes are reduced to increase integration density, then more components can be integrated, but fabrication processes become more difficult
Solution Approach 1:
The conductive via structures are designed to be self-aligned with the bonding targets on the chip and substrate. The protruding ends of the via structures automatically provide alignment references for the bonding process, eliminating the need for complex alignment procedures and making the fabrication process easier despite reduced feature sizes.
Solution Approach 2:
The patent changes the geometric parameters of the conductive via structures, specifically creating a width profile that is narrower at the top and wider at the bottom. This parameter change allows the via structures to maintain mechanical strength while reducing the lateral space required, enabling smaller feature sizes without proportionally increasing fabrication difficulty.
Data Source
AI summary
A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conductive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.