Interposer Via Polygonal Packing for Semiconductor Package Adaptability

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Solution Overview

Problem

The existing methods for fabricating semiconductor packages require customized interposer layers and photomasks for each package, leading to increased costs and inefficiencies due to the need for different connection configurations.

Innovation Solution

A method involving an interposer layer with through interposer vias patterned to form repetitive polygonal-packing units, which are connected to redistribution layers and semiconductor chips, allowing for adaptable connection configurations with a single photomask, enhancing compatibility and reducing fabrication costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If customized interposer layers with different connection configurations are used for each semiconductor package, then the adaptability to different package requirements is improved, but the device complexity and fabrication cost increase due to needing different photomasks for each package

Engineering Contradiction:

Improveadaptability to different package requirementsVSAvoidfabrication complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single standardized interposer layer with a regular array of through interposer vias that can serve multiple different semiconductor package configurations. Instead of creating customized interposer layers for each package type, the standardized design with uniformly spaced vias allows flexible routing and connection to various chip layouts, enabling one interposer design to fulfill multiple package requirements without redesign

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes parameter changes by varying the routing paths, conductor traces, and connection configurations on the interposer layer while maintaining the same standardized via array structure. By changing the routing parameters and connection topology rather than the fundamental interposer geometry, different package configurations can be achieved using the same base interposer design, thus avoiding the need for different photomasks

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If customized interposer layers with different connection configurations are used for each semiconductor package, then the adaptability to different package requirements is improved, but the manufacturing cost increases due to the need for different photomasks

Engineering Contradiction:

Improveadaptability to different package requirementsVSAvoidfabrication cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The standardized interposer layer design with a regular via array serves as a universal platform that can be used across multiple package types. This universality eliminates the need to manufacture different photomasks for different packages, as the same photomask can be reused to create the standardized via pattern that adapts to various package configurations through different routing schemes

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs copying by replicating the same standardized interposer layer design with identical via patterns across multiple packages. Instead of creating unique interposer designs for each package, the same master pattern is copied and reused, significantly reducing photomask fabrication costs while maintaining adaptability through flexible routing implementations

Inventive Principle:

Principle #26Copying

3Productivity

If through interposer vias are patterned to form repetitive polygonal-packing units, then the manufacturing efficiency is improved by using a single photomask, but the connection configuration flexibility may be limited

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidconnection configuration flexibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent resolves the contradiction by transitioning from two-dimensional via placement to three-dimensional routing solutions. The repetitive polygonal-packing units provide a regular 2D pattern that is easy to manufacture, while flexible 3D routing paths and multi-layer conductor traces enable diverse connection configurations to emerge from this standardized base structure

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10037937B2Method for forming semiconductor package

Publication Date: 2018.07.31 NAN YA TECH

AI summary

A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.