Interposer Via Package Structure for Fine-Pitch Self-Aligned Bonding
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable packages with high integration density as feature sizes continue to decrease, making fabrication processes increasingly difficult.
Innovation Solution
A package structure is formed using a carrier substrate and interposer substrate with conductive via structures that reduce the size of conductive bumps by eliminating the need for under-bump metallurgy, allowing for self-aligned joints and fine-pitch routings, thereby improving design flexibility and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional under-bump metallurgy is used, then bonding reliability is improved, but device size and manufacturing complexity increase
Solution Approach 1:
The patent extracts and eliminates the under-bump metallurgy layer from the conventional bonding structure. By directly bonding the conductive bump to the pad structure without intermediate metallurgy layers, the invention simplifies the manufacturing process while maintaining bonding reliability through direct metal-to-metal contact and controlled bonding parameters.
Solution Approach 2:
The pad structure is designed to serve multiple functions: it provides both the bonding surface and the electrical connection pathway. The conductive via structure integrates both mechanical support and electrical conduction functions, eliminating the need for separate metallurgy layers that would otherwise be required for these functions.
2Productivity
If feature sizes are reduced to increase integration density, then more components are integrated into a given area, but fabrication difficulty increases
Solution Approach 1:
The bonding process is segmented into distinct stages: pad structure formation, conductive via formation, and direct bump bonding. This segmentation allows each process to be optimized independently, enabling precise control at smaller feature sizes while maintaining overall manufacturing feasibility.
Solution Approach 2:
The invention changes the bonding parameters by eliminating the metallurgy layer thickness variable and focusing control on bump size, pad geometry, and bonding conditions. This parameter simplification makes the process more controllable at reduced feature sizes, as fewer process variables need to be managed simultaneously.
3Length of moving object
If conductive bump size is reduced, then fine-pitch routings are enabled, but manufacturing precision requirements increase
Solution Approach 1:
The pad structure is formed with precise dimensions and positioning before the bump bonding process. The conductive via structures are pre-formed with controlled geometry and location. These preliminary actions establish reference features that guide the subsequent bump placement, enabling high precision at reduced bump sizes through cumulative process control rather than relying solely on the final bonding step.
Data Source
AI summary
A package structure is provided. The package structure includes an interposer substrate comprising an insulating structure, a conductive pad, a first conductive via structure, and a second conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a conductive pillar connected to the second end portion of the second conductive via structure. The second end portion extends into the conductive pillar. The package structure includes a solder bump connected to the conductive pillar. The solder bump extends into the conductive pillar.