Interposer Structure With Compressive Layers for Warpage Control
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Solution Overview
Problem
Semiconductor wafers and packages experience warpage due to differences in thermal expansion coefficients, leading to reliability issues, especially as the volume of metal interconnect patterns increases, causing excessive warpage and potential deformation during temperature changes.
Innovation Solution
The warpage is controlled by adjusting the ratio of the total volume of lower conductive pads to the metal interconnect pattern and applying compressive stress to the insulating and protection layers, ensuring the interposer remains within a predetermined warpage range through the use of inorganic and organic materials and specific layer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the volume of metal interconnect patterns is increased, then electrical connectivity and signal integrity are improved, but warpage of the interposer increases due to differential thermal expansion
Solution Approach 1:
The patent applies compressive stress to the insulating layer and protection layers to counterbalance the tensile stress generated by metal interconnect patterns during thermal expansion. By changing the stress state of the dielectric layers from neutral or tensile to compressive, the overall warpage of the interposer is reduced while maintaining the metal interconnect volume for electrical performance
Solution Approach 2:
The patent uses composite material structures consisting of metal interconnect patterns embedded in insulating layers with specific stress characteristics. The combination of metal (high thermal expansion) and stressed dielectric materials (compressive stress) creates a composite structure where the stress compensation reduces warpage while maintaining electrical connectivity
2Strength
If the thickness of protection layers is increased, then mechanical protection and stress control are improved, but manufacturing complexity and process precision requirements increase
Solution Approach 1:
The patent specifies that the protection layer thickness should be in the range of about 10% to about 50% of the insulating layer thickness. By optimizing this thickness parameter, the patent achieves sufficient mechanical protection and stress control without excessive layer thickness that would complicate manufacturing processes
Solution Approach 2:
The patent applies different material properties and stress characteristics to different layers (insulating layer vs. protection layer) based on their specific functions. The insulating layer provides electrical isolation with compressive stress, while the protection layer provides mechanical protection with optimized thickness, creating local quality optimization throughout the structure
3Shape
If compressive stress is applied to insulating and protection layers, then warpage is reduced, but manufacturing precision and stress control requirements increase
Solution Approach 1:
The patent specifies that the compressive stress in the protection layer should be in the range of about 50 MPa to about 500 MPa, and the insulating layer stress should be coordinated to achieve overall warpage reduction. By defining specific stress parameter ranges, the patent makes the stress control process more predictable and manufacturable
Solution Approach 2:
The patent measures and controls the warpage of the interposer to verify that the compressive stress applied to the dielectric layers is achieving the desired warpage reduction. This feedback approach allows manufacturing processes to adjust stress parameters to meet target warpage specifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage across various temperature sections, enhancing the reliability of both the interposer and semiconductor packages by maintaining a stable shape and improving signal and power integrity.
Implementation Method 1
At least one of the insulating layer and the first lower protection layer have compressive stress
Implementation Method 2
warpage may occur in the interposer and/or the semiconductor package due to a difference between coefficients of thermal expansion (CTE) of components forming the interposer or the semiconductor package
Data Source
AI summary
An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.