Semiconductor Package Interposer Warpage Prevention
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Solution Overview
Problem
Flip-chip packaging technologies face issues due to CTE mismatch between semiconductor chips and packaging substrates, leading to delamination, warpage, and reduced reliability, as well as inefficiencies in the underfilling process that increase production time and risk of electrical connection failures.
Innovation Solution
A semiconductor package and fabrication method that uses a carrier with interposers encapsulated by an encapsulant, where a redistribution layer is formed on both the interposers and the encapsulant, allowing for a planar surface and eliminating the need for multiple underfilling processes, thereby preventing warpage and improving electrical connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon interposer with small thickness is used to overcome CTE mismatch, then the CTE mismatch problem between chip and packaging substrate is resolved, but warpage easily occurs during reflow process reducing planarity and electrical connection reliability
Solution Approach 1:
The patent changes the thickness parameter of the interposer from small (4 mil) to large (greater than 4 mil), which fundamentally alters the mechanical properties and warpage behavior during reflow processing, thereby maintaining planarity while resolving CTE mismatch
Solution Approach 2:
The patent applies underfill material between the interposer and packaging substrate before the reflow process to provide mechanical support and cushioning, preventing warpage and cracking of conductive bumps during the thermal cycling process
2Reliability
If two underfilling processes are performed for each silicon interposer to form underfill between interposer and packaging substrate and between interposer and chip, then proper encapsulation is achieved, but process time is significantly increased reducing productivity
Solution Approach 1:
The patent merges the two separate underfilling processes into a single underfilling operation by applying underfill material that simultaneously encapsulates both the interposer-packaging substrate interface and the interposer-chip interface, thereby maintaining encapsulation quality while halving the process time
Solution Approach 2:
The underfill material is designed to serve multiple functions simultaneously: it acts as encapsulation for both interfaces, provides mechanical support, and enables proper bonding, eliminating the need for separate underfilling steps for each interface
3Volume of moving object
If silicon interposer has small thickness such as 4 mil, then packaging size is reduced, but underfill easily creeps up to contaminate redistribution layer resulting in electrical connection failure
Solution Approach 1:
The patent increases the interposer thickness parameter from 4 mil to greater than 4 mil, which provides sufficient barrier height to prevent underfill creep while maintaining compact packaging dimensions, thus preventing contamination of the redistribution layer
Data Source
AI summary
A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.