Interposer Mounted Wiring Board Thermal Stress Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of multiple semiconductor chips on an organic substrate using a silicon interposer leads to thermal expansion mismatch issues, causing warpage and reliability problems during temperature cycling tests, and heat management challenges due to shared heat spreaders, which restrict the use of high-performance logic chips.
Innovation Solution
An interposer mounted wiring board design with interposers having coefficients of thermal expansion matching those of the chips, mounted on both surfaces of the board, with a wiring board interposed between them to minimize thermal stress and isolate heat sources, allowing for separate heat management of logic and memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated on an organic substrate using a silicon interposer, then the system functionality and performance are improved, but thermal expansion mismatch causes warpage and reliability problems during temperature cycling tests
Solution Approach 1:
The patent introduces a resin layer as an intermediary substance between the silicon interposer and the organic substrate. This resin layer has a coefficient of thermal expansion that is lower than that of the silicon interposer, acting as a buffer to reduce the thermal expansion mismatch. The resin layer absorbs the differential thermal stress generated during temperature cycling, preventing warpage and improving the reliability of the integrated structure.
Solution Approach 2:
The patent modifies the thermal expansion characteristics of the interposer assembly by selecting a resin material with specific thermal expansion properties. The resin layer's coefficient of thermal expansion is deliberately chosen to be lower than that of silicon, creating a gradient that compensates for the mismatch between the silicon interposer and the organic substrate during temperature variations.
2Temperature
If a heat spreader is used to release heat from high-performance logic chips, then heat dissipation is improved, but the heat affects memory chips mounted on the same interposer
Solution Approach 1:
The patent divides the thermal management system into separate zones by mounting the logic chip and memory chip on opposite surfaces of the silicon interposer. This spatial segmentation allows the heat spreader to be positioned only over the logic chip area, confining the heat dissipation function to the high-performance logic chip while preventing thermal interference with the memory chip mounted on the opposite side.
Solution Approach 2:
The patent transitions from a planar arrangement where both chips would share the same thermal zone to a three-dimensional configuration using the interposer thickness as a separating dimension. By mounting chips on opposite surfaces of the interposer, the design utilizes the vertical dimension to physically isolate the thermal fields of the logic chip and memory chip, allowing independent thermal management.
3Device complexity
If the same interposer is used for both logic chips and memory chips, then manufacturing complexity is reduced, but heat from logic chips damages or degrades memory chip performance
Solution Approach 1:
The patent segments the thermal management function by positioning the heat spreader to cover only the logic chip area on one surface of the interposer. This selective placement creates thermal zones that are spatially separated, allowing the logic chip to receive active heat dissipation while the memory chip on the opposite side operates in a thermally neutral environment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces thermal expansion mismatch and warpage, enhances reliability in temperature cycling tests, and allows for the use of high-performance logic chips without affecting memory chips, improving overall system performance and flexibility.
Implementation Method 1
a first interposer electrically connected to a first wiring layer on a first surface of the wiring board and having a value of a coefficient of thermal expansion, the value being equal or close to a value of a coefficient of thermal expansion of a first electronic component to be mounted thereon
Implementation Method 2
with a wiring board interposed between them to minimize thermal stress and isolate heat sources, allowing for separate heat management of logic and memory chips
Data Source
AI summary
An interposer mounted wiring board includes a wiring board including outermost wiring layers respectively on both surfaces thereof, the outermost wiring layers being electrically connected to each other through an inside of the board, and first and second interposers electrically connected to the outermost wiring layers on the both surfaces of the board, respectively. Each of the first and second interposers has a value of a coefficient of thermal expansion (CTE), the value being equal or close to a value of a CTE of a corresponding one of first and second electronic components to be mounted respectively on the first and second interposers. The base member of each of the interposers is preferably formed of silicon, and the base member of the wiring board is preferably formed of resin. Further, the electronic components are mounted respectively on surfaces of the interposers and thus form a semiconductor device, the surfaces being opposite to the surfaces of the interposers facing the wiring board.