Interposer Wiring Layout Using Unused Space for Die Interconnects
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Solution Overview
Problem
Existing interposer implementations in semiconductor devices result in underutilization of available space, leading to inefficiencies and increased costs due to underutilized wiring areas and complex assembly processes, particularly in high computational complexity applications.
Innovation Solution
Relocate global interconnection layers from processor dies to underutilized spaces within the interposer, reducing the number of fabrication steps and leveraging unused areas for cost-effective and efficient semiconductor packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If global interconnection layers are kept on processor dies, then wiring capacity is sufficient, but interposer space is underutilized and fabrication costs increase
Solution Approach 1:
The patent extracts the global interconnection layers from the processor die and relocates them to the interposer substrate. This extraction resolves the space underutilization problem by placing wiring structures in the previously empty interposer area, while also simplifying processor die fabrication by removing complex global wiring requirements.
Solution Approach 2:
The patent transitions the location of global interconnection layers from a two-dimensional plane on the processor die surface to a three-dimensional redistribution across the interposer substrate. This dimensional relocation allows for optimized wiring routes and better space utilization without increasing processor die complexity.
2Productivity
If interposer area is increased for high computational complexity applications, then wiring capacity increases, but space utilization drops to less than five to ten percent
Solution Approach 1:
The interposer substrate is designed to serve multiple functions: it acts as a mechanical support structure, provides electrical interconnections between processor dies, and hosts the global interconnection layers. This multi-functionality ensures that the entire interposer area is productively utilized, achieving high space utilization alongside high wiring capacity.
3Ease of operation
If conventional interposer structures are used, then assembly is simplified, but manufacturing precision requirements increase due to underutilized wiring areas
Solution Approach 1:
The patent implements localized high-density wiring regions on the interposer substrate precisely where processor dies are mounted, while maintaining lower wiring density in other areas. This local quality approach ensures high manufacturing precision is applied only where needed, reducing overall precision requirements while maintaining assembly simplicity.
Data Source
AI summary
A structure is disclosed. The structure can include a first processor die and an interposer. The first processor die comprises a first processor core and a second processor core. The first processor die is disposed above and bonded to the interposer. The interposer comprises a first plurality of conductors electrically connecting the first processor core and the second processor core. The first processor core and the second processor core communicate with each other through the first plurality of conductors.