Interrupt Blocking Unit for Secure State Non-Secure Interrupt Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In processors that support secure and non-secure states, non-secure interrupts can corrupt registers when processed in a secure state, leading to thread crashes, and existing solutions that use Supervisory Calls to mitigate this introduce significant latency.
Innovation Solution
Implementing an interrupt blocking unit that blocks non-secure interrupts based on a processor operating mode signal, using hardware registers to store mask flags or a block enable signal, allowing for selective blocking of individual or all non-secure interrupts when the processor is in a secure state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If non-secure interrupts are allowed to be processed in secure state, then interrupt response time is improved, but register corruption and system stability deteriorate
Solution Approach 1:
The interrupt blocking mechanism dynamically adapts to the processor's security state. When in secure state, non-secure interrupts are blocked; when in non-secure state, they are allowed. This dynamic switching resolves the contradiction by making the interrupt handling behavior contingent on the current security context, preventing register corruption while maintaining responsiveness when safe.
Solution Approach 2:
An interrupt blocking unit is introduced as an intermediary between the interrupt source and the processor. This unit monitors the security state and selectively blocks or passes through non-secure interrupts based on whether the processor is in a secure or non-secure state, thereby preventing harmful interrupts from reaching the processor during secure operations while allowing them during non-secure operations.
2Reliability
If Supervisory Calls are used to mitigate register corruption, then system stability is improved, but processing latency increases significantly
Solution Approach 1:
The system performs preliminary action by blocking non-secure interrupts at the hardware level before they can cause register corruption. The interrupt blocking unit proactively prevents harmful interrupts from reaching the processor during secure state, eliminating the need for corrective Supervisory Calls and the associated latency overhead.
Solution Approach 2:
The software-based Supervisory Call mechanism is replaced with a hardware-level interrupt blocking mechanism. Instead of using software traps and mode switches to prevent register corruption, the patent implements a hardware unit that directly blocks non-secure interrupts at the electrical level, significantly reducing the latency associated with software-based protection mechanisms.
3Reliability
If all non-secure interrupts are blocked in secure state, then register corruption is prevented, but legitimate interrupt handling capability deteriorates
Solution Approach 1:
The interrupt blocking mechanism is segmented to distinguish between secure and non-secure interrupt sources. Rather than blocking all interrupts uniformly, the system specifically targets non-secure interrupts for blocking during secure state while leaving secure interrupts unaffected. This selective approach preserves register integrity while maintaining the ability to handle legitimate secure interrupts.
Solution Approach 2:
The interrupt blocking behavior is localized to non-secure interrupts during secure state, while secure interrupts maintain their normal handling characteristics. This local differentiation ensures that only the problematic non-secure interrupts are blocked, preserving the processor's ability to respond to legitimate secure interrupts and maintaining overall interrupt handling versatility.
Data Source
AI summary
One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a processor, a first interrupt source configured to generate a first non-secure interrupt, and an interrupt blocking unit configured to block the first non-secure interrupt responsive to the processor operating in a secure state.