Hardware Interrupt Synchronization for Call Delay Measurement

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Solution Overview

Problem

Conventional methods for measuring call delay time in MOS measuring devices are prone to measurement errors due to the difficulty in synchronizing the replaying and recording parts, leading to unreliable results that vary with operator performance.

Innovation Solution

A method using hardware interrupts to synchronize the replaying and recording parts, where CPUs connected via ready and starting interrupt signal lines manage the transfer of audio data and calculate the call delay time, excluding ready process times from the measurement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If manual operation is used to press replay and record buttons simultaneously, then the measuring device can be operated, but measurement precision deteriorates due to timing errors of tens of milliseconds

Engineering Contradiction:
Improvemanual operationVSAvoidcall delay time measurement
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent replaces the mechanical manual button-pressing system with an automated interrupt-based hardware system. The replay and record operations are triggered by interrupt signals from the network interface card, eliminating the need for manual coordination and achieving precise timing synchronization automatically.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an interrupt signal as an intermediary mechanism between the network interface card and the CPU. This interrupt signal automatically triggers the replay and record operations at the precise moment when audio data becomes available, serving as a mediator that eliminates timing errors caused by manual operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If manual synchronization method is used, then device complexity is low, but reliability deteriorates due to operator-dependent measurement variations

Engineering Contradiction:
Improvesynchronization mechanismVSAvoidmeasurement reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent replaces the manual operator-based synchronization system with an automated interrupt-driven hardware system. The reliability is improved by eliminating human factors such as reaction time variations and operator skill differences, while the increase in device complexity is minimal since it utilizes existing interrupt capabilities of the CPU and network interface card.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If ready process time is included in measurement, then measurement process is simple, but measurement precision deteriorates due to inclusion of non-network delay components

Engineering Contradiction:
Improvemeasurement processVSAvoidactual call delay time
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent extracts and excludes the ready process time from the call delay time measurement. By using interrupt signals to mark the exact start and end points of actual audio data transmission, the system separates the relevant network delay components from the irrelevant ready process components, achieving precise measurement of only the actual call delay time.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9219773B2Method of measuring call delay time
Publication Date: 2015.12.22 INNOWIRELESS
  • US9219773B2 patent drawing
  • US9219773B2 patent drawing
  • US9219773B2 patent drawing

AI summary

A method of measuring a call delay time by synchronizing times of a replaying part and a recording part in a call delay time measuring device using an interrupting hardware method. The method includes reading an original WAV file when a replaying CPU receives a command, waiting for writing to a DAC buffer of a replaying CODEC, transferring a signal of recording-ready to a recording CPU, generating a recording WAV file by the recording CPU, waiting for reading from an ADC buffer of a recording CODEC, transferring a signal of complete recording-ready to the replaying CPU, recording the original WAV file, replaying the original WAV file and simultaneously transferring a signal of recording-start to the recording CPU, and reading audio data from the ADC buffer of the recording part by the recording CPU and recording the audio data to the recording WAV file.