Interrupt Controller Clock Gating for Low-Power Signal Capture

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Solution Overview

Problem

Conventional interrupt controllers face challenges in managing interrupt signals, particularly safety faults, while minimizing power consumption, especially when transitioning to low power modes, risking the omission of critical signals.

Innovation Solution

An interrupt controller with a control circuit that automatically generates a controller clock signal from an external clock signal upon receipt of an interrupt signal, ensuring timely delivery of output interrupt signals without continuous clock supply, using techniques like clock gating to conserve power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the interrupt controller operates continuously with a clock signal supplied, then all interrupt signals are processed without omission, but power consumption increases

Engineering Contradiction:
Improveinterrupt signal processing completenessVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by switching the interrupt controller between active and low-power states. The controller operates actively only when interrupt signals are present, and transitions to low-power mode when no interrupts are pending, thereby achieving periodic operation cycles that balance reliability and energy efficiency

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The interrupt controller monitors its own interrupt signal status and autonomously determines when to switch between operational modes. The controller uses its internal interrupt signal detection capability to self-regulate its power state without external control, entering low-power mode when no interrupts are pending and activating when interrupts are detected

Inventive Principle:
Principle #25Self-service

2Use of energy by moving object

If the interrupt controller enters low power mode to reduce consumption, then power consumption decreases, but interrupt signals may be missed

Engineering Contradiction:
Improvepower consumptionVSAvoidinterrupt signal processing completeness
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent implements preliminary action by maintaining the capability to detect interrupt signals even in low-power mode. The controller prepares for potential interrupts by keeping minimal detection functionality active, allowing it to quickly resume full operation when an interrupt occurs, thus preventing any interrupt signals from being missed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interrupt controller uses feedback from its interrupt signal input to control its power state. The detection of interrupt signals provides feedback that triggers the controller to exit low-power mode and resume full operation, ensuring that the system responds appropriately to external events while maintaining energy efficiency during idle periods

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11550744B2Interrupt controller and method of managing an interrupt controller
Publication Date: 2023.01.10 STMICROELECTRONICS (GRENOBLE 2) SAS
  • US11550744B2 patent drawing
  • US11550744B2 patent drawing
  • US11550744B2 patent drawing

AI summary

In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.