Interrupt Control Circuit for Image Processing CPU Load Reduction
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Solution Overview
Problem
The existing interrupt control systems do not adequately reduce the CPU load, as they require the CPU to monitor the main memory for interrupts, leading to inefficiencies in image data transfer.
Innovation Solution
An image processing device with a data transfer unit for each interrupt factor, including a first interrupt control unit for outputting interrupt signals and a second interrupt control unit for notifying the CPU when data transfer is complete, allowing for efficient data transfer and reduced CPU load by minimizing interrupt processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU monitors the main memory to detect interrupts, then interrupt detection is achieved, but the CPU load is not sufficiently reduced
Solution Approach 1:
The patent introduces a dedicated interrupt control circuit as an intermediary between the main memory and the CPU. This circuit autonomously monitors the main memory for interrupt conditions and only notifies the CPU when actual interrupt factors are detected, eliminating the need for the CPU to continuously monitor memory and thereby reducing CPU load while maintaining reliable interrupt detection
Solution Approach 2:
The interrupt control circuit performs self-service by autonomously detecting interrupt conditions in the main memory and filtering out non-interrupt factors before notifying the CPU. This self-monitoring capability allows the system to maintain interrupt detection functionality without requiring CPU intervention for memory monitoring
2Productivity
If DMA transfer is used to reduce CPU load, then data transfer efficiency improves, but interrupt processing during transfer increases CPU involvement
Solution Approach 1:
The interrupt control circuit uses feedback mechanisms to monitor the status of DMA transfers and interrupt factors in the main memory. By continuously checking transfer completion status and interrupt factor registers, the circuit can determine when data transfer is complete and when actual interrupt factors exist, enabling efficient coordination between DMA operations and interrupt handling without increasing CPU load
Data Source
AI summary
The present invention provides CPU load reduction and a method of efficient image data transfer. An image processing device, which comprises an image generating unit (203) which further comprises a plurality of processing units which process a plurality of instances of image information and in where the image generating unit (203) transfers accumulated data for each interrupt factor, comprises: data transfer units for each factor (208-212) which accept the interrupts from the image generating unit (203) for each interrupt factor and transfer the data for each interrupt factor, and notifies a CPU (207) of the interrupt when the transfer of the data to be transferred for each interrupt factor is completed; and a communication line (1) which is connected to the image generating unit (203) and the data transfer units for each factor (208-212).