Interrupt Control Circuit Timing Jitter Reduction
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Solution Overview
Problem
In time-triggered communication systems, particularly in vehicle-mounted devices, timer interrupts can cause delays in processing due to inhibition of multiple interrupt processing and varying interrupt priority levels, leading to difficulties in achieving high-accuracy real-time control and inadequate CPU load reduction.
Innovation Solution
A semiconductor data processing device with an interrupt control circuit that delays the start of interrupt processing by a predetermined reservation time when a timer interrupt request is received, inhibiting other interrupt requests during this period to ensure timely processing according to a predetermined schedule, thereby reducing timing variations and maintaining synchronization with a common network time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple interrupt processing is inhibited and interrupt priority levels are used, then interrupt processing can be controlled, but timing variations occur and processing delays increase
Solution Approach 1:
The patent applies preliminary action by setting a reserved time period in advance before the scheduled processing time. When a timer interrupt request is received, the system determines whether to inhibit other interrupt requests based on whether the current time falls within this pre-established reserved time period. This allows the system to proactively prevent timing variations and processing delays by controlling interrupt processing before they occur, ensuring that scheduled processing happens at the correct time without interference from other interrupts.
2Manufacturing precision
If timer interrupt processing is performed at predetermined times, then time-triggered communication is enabled, but CPU load increases due to processing overhead
Solution Approach 1:
The patent applies self-service by enabling the interrupt control circuit to autonomously determine whether to inhibit other interrupt requests based on the current time and the reserved time period, without requiring complex CPU intervention. The circuit automatically compares the current time with the reserved time period and makes the inhibition decision independently. This reduces the processing overhead and CPU load while maintaining precise timing for time-triggered communication, as the time-critical decisions are handled by the dedicated circuit rather than the general-purpose CPU.
3Measurement precision
If interrupt inhibition is applied during reserved time period, then timing accuracy is improved, but system responsiveness to other interrupts decreases
Solution Approach 1:
The patent applies local quality by making the interrupt inhibition selective and context-dependent rather than universal. The interrupt control circuit evaluates each interrupt request individually and determines whether to inhibit it based on whether the current time falls within the reserved time period for scheduled processing. This localized approach ensures that timing accuracy is improved only when necessary (during the reserved time period), while maintaining system responsiveness to other interrupts when the scheduled processing is not active, thus balancing timing precision with overall system responsiveness.
Data Source
AI summary
The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request.