Interrupt Control Logic for Clock Domain Signal Clearance
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Solution Overview
Problem
In chip design, signal transmission between different clock domains can lead to metastable states, causing uncertain chip operation and potential failure, particularly when multiple peripheral devices in one clock domain transmit interrupt signals to a processor in another clock domain, as existing solutions fail to properly handle the clearance of interrupt signals across domains, resulting in incorrect operations.
Innovation Solution
An interrupt control device and method that includes interrupt sharing logic to combine original interrupt signals and processing logic to generate a processed interrupt signal, which is used to execute an interrupt service routine, with the processor sending a control signal to block further interrupts and output an interrupt clear signal to negate the original signals, ensuring proper clearance detection and re-generation of the processed signal after clearance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt signals from multiple peripheral devices in the first clock domain are transmitted directly to the processor in the second clock domain without proper clearance handling, then the interrupt response speed is improved, but incorrect operations occur due to metastable states and improper clearance detection
Solution Approach 1:
An interrupt control device is introduced as an intermediary between the first clock domain (peripheral devices) and the second clock domain (processor). This device includes clearance detection logic that monitors interrupt signals from multiple peripheral devices and properly detects their clearance states before forwarding to the processor, thereby preventing incorrect operations while maintaining interrupt response speed.
Solution Approach 2:
The interrupt control device implements feedback mechanisms by continuously monitoring the state of interrupt signals from peripheral devices and adjusting its output accordingly. The clearance detection logic provides feedback about the current interrupt state to control signal generation, ensuring that interrupt signals are only forwarded when properly cleared, thus maintaining operational correctness.
2Reliability
If signal synchronizers are used to synchronize interrupt signals between clock domains, then metastable states are reduced, but the complexity of the interrupt control system increases and clearance detection becomes more difficult
Solution Approach 1:
The patent combines signal synchronization and clearance detection functions into a single integrated interrupt control device. By merging these functions, the system avoids the complexity of separate synchronizers and clearance detection circuits, while still achieving reliable signal stability and proper clearance handling across clock domains.
Solution Approach 2:
The interrupt control device performs multiple functions simultaneously: it synchronizes signals across clock domains, detects interrupt clearances, and controls signal forwarding. This multi-functional approach reduces overall system complexity compared to using separate dedicated circuits for each function.
3Measurement precision
If the processor continuously monitors all interrupt signals to detect clearance, then accurate clearance detection is achieved, but the processor workload increases and interrupt handling efficiency decreases
Solution Approach 1:
The interrupt control device segments the clearance detection function from the processor by implementing dedicated clearance detection logic for each peripheral device interface. This allows accurate monitoring of individual interrupt signal clearances without requiring the processor to continuously check all interrupt sources, thereby maintaining detection accuracy while improving overall interrupt handling efficiency.
Data Source
AI summary
An interrupt control device between clock domains is provided. An interrupt sharing logic is configured to receive one or more original interrupt signals and generate a combined interrupt signal. An interrupt processing logic is configured to output a processed interrupt signal to a processor according to the combined interrupt signal, so that the processor executes an interrupt service routine. When the interrupt service routine is executed, the processed interrupt signal changes to be disabled; before the interrupt service routine is completed, the processor outputs an interrupt clear signal to change the respective interrupt signal to be negated. After the interrupt processing logic detects that interrupt signal has been cleared successfully, the interrupt processing logic will generate the processed interrupt signal according to the combined interrupt signal again.